PFS154 datasheet(5/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 5 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

6.27. Comparator Selection Register (gpcs), IO address = 0x19......................................................66

6.28. PWMG0 control Register (pwmg0c), IO address = 0x20 .........................................................67

6.29. PWMG0 Scalar Register (pwmg0s), IO address = 0x21..........................................................67

6.30. PWMG0 Counter Upper Bound High Register (pwmg0cubh), IO address = 0x24 ...................67

6.31. PWMG0 Counter Upper Bound Low Register (pwmg0cubl), IO address = 0x25 .....................67

6.32. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 .......................................67

6.33. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 .........................................68

6.34. PWMG1 control Register (pwmg1c), IO address = 0x26 .........................................................68

6.35. PWMG1 Scalar Register (pwmg1s), IO address = 0x27..........................................................68

6.36. PWMG1 Counter Upper Bound High Register (pwmg1cubh), IO address = 0x2a ...................69

6.37. PWMG1 Counter Upper Bound Low Register (pwmg1cubl), IO address = 0x2b .....................69

6.38. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 .......................................69

6.39. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29 .........................................69

6.40. PWMG2 control Register (pwmg2c), IO address = 0x2c .........................................................69

6.41. PWMG2 Scalar Register (pwmg2s), IO address = 0x2d..........................................................70

6.42. PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30 ...................70

6.43. PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31 .....................70

6.44. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2e .......................................70

6.45. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2f ..........................................70

Instructions .........................................................................................................................71

7.1.

Data Transfer Instructions .......................................................................................................72

7.2.

Arithmetic Operation Instructions ............................................................................................75

7.3.

Shift Operation Instructions .....................................................................................................77

7.4.

Logic Operation Instructions....................................................................................................78

7.5.

Bit Operation Instructions ........................................................................................................80

7.6.

Conditional Operation Instructions ..........................................................................................81

7.7.

System control Instructions .....................................................................................................82

7.8.

Summary of Instructions Execution Cycle ...............................................................................83

7.9.

Summary of affected flags by Instructions ...............................................................................84

7.10. BIT definition ...........................................................................................................................84

Code Options ......................................................................................................................85

Special Notes ......................................................................................................................86

9.1.

Warning ..................................................................................................................................86

9.2.

Using IC ..................................................................................................................................86

9.2.1

IO pin usage and setting..............................................................................................86

9.2.2

Interrupt.......................................................................................................................87

9.2.3

System clock switching................................................................................................87

9.2.4

Watchdog ....................................................................................................................87

9.2.5

TIMER16 time out........................................................................................................88

9.2.6

IHRC Calibration .........................................................................................................88

9.2.7

LVR .............................................................................................................................88

9.2.8

Program writing ...........................................................................................................89

9.3.

Using ICE................................................................................................................................91

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