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PFS154 Datasheet(PDF) 61 Page - PADAUK Technology.

Part # PFS154
Description  8bit MTP Type IO controller
PDF  91 Pages
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Manufacturer  PADAUK [PADAUK Technology.]
Direct Link  http://www.padauk.com.tw/
Logo PADAUK - PADAUK Technology.

PFS154 Datasheet(HTML) 61 Page - PADAUK Technology.

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PFS154
8bit MTP Type IO Controller
©Copyright 2020, PADAUK Technology Co. Ltd
Page 61 of 91
PDK-DS-PFS154_CN_V105 –Jun. 9, 2020
6.8. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
Description
7 - 5
-
-
Reserved.
4
0
WO
Timer16 edge selection.
0 : rising edge to trigger interrupt
1 : falling edge to trigger interrupt
3 - 2
00
WO
PB0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
1 - 0
00
WO
PA0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
6.9. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
7 - 6
11
WO
Enable PA7~PA6 digital input and wake up event.
1 / 0 : enable / disable.
These bits should be set to low to prevent leakage current when external crystal oscillator is
used. If these bits are set to low, PA7~PA6 can NOT be used to wake-up the system.
5 - 3
111
WO
Enable PA5~PA3 digital input and wake up event.
1 / 0 : enable / disable.
If these bits are set to low, PA5~PA3 can NOT be used to wake-up the system.
2 - 1
-
-
Reserved.
0
1
WO
Enable PA0 digital input, wake up event and interrupt request.
1 / 0 : enable / disable.
This bit can be set to low to disable wake up from PA0 toggling and interrupt request from
this pin.
6.10. Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset
R/W
Description
7 - 1
0xFF
WO
Enable PB7~PB1 digital input and wake up event.
1 / 0 : enable / disable.
When this bit is “0”, PA7~PA1 can NOT be used to wake-up the system.
0
WO
Enable PA0 digital input, wake up event and interrupt request.
1 / 0 : enable / disable.
This bit can be set to low to disable wake up from PA0 toggling and interrupt request from
this pin.
6.11. Port A Data Registers (pa), IO address = 0x10
Bit
Reset
R/W
Description
7 - 0
0x00
R/W
Data registers for Port A.



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