PFS154 datasheet(31/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 31 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

5.4.5

System Clock and LVR levels

The clock source of system clock comes from IHRC, ILRC or EOSC, the hardware diagram of system clock in

the PFS154 is shown as Fig. 3.

Fig. 3: Options of System Clock

User can choose different operating system clock depends on its requirement; the selected operating system

clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be

checked during compilation, and the lowest LVR levels can be chosen for different operating frequencies.

Please refer to Section 4.1.

5.4.6

System Clock Switching

After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock

at any time to optimize the system performance and power consumption. Basically, the system clock of

PFC154 can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time; system

clock will be the new one after writing to clkmd register immediately. Please notice that the original clock

module can NOT be turned off at the same time as writing command to clkmd register. The examples are

shown as below and more information about clock switching, please refer to the “Help” -> “Application Note”

-> “IC Introduction” -> “Register Introduction” -> CLKMD”.

Case 1: Switching system clock from ILRC to IHRC/2

…

system clock is ILRC

CLKMD.4

turn on IHRC first to improve anti-interference ability

CLKMD

0x34

；

switch to IHRC/2

，ILRC CAN NOT be disabled here

CLKMD.2

；

if need, ILRC CAN be disabled at this time

…

Case 2: Switching system clock from ILRC to EOSC

…

system clock is ILRC

CLKMD

0xA6

；

switch to IHRC

，ILRC CAN NOT be disabled here

CLKMD.2

；

ILRC CAN be disabled at this time

…

clkmd

System

clock

CLK

÷2, ÷4, ÷8,

÷16, ÷32, ÷64

÷1, ÷4, ÷16

IHRC

ILRC

÷1, ÷2, ÷4, ÷8

EOSC

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