TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

10

POST OFFICE BOX 655303

XTAL

OSC

TMS320

DSP

Divide

by 135

Commercial

External

Front-End

Full-Duplex

Split-Band

Filters†

TA Register

(5 bits)

TA’ Register

(6 bits)

(2’s compl)

Adder/

Subtractor

(6 bits)

Divide by 2

TB Register

(6 bits)

[TA = 9 (1)]

[TA = 18 (2)]

(6 bits)

TX Counter A

[TB = 40; 7.2 kHz

[TB = 36; 8.0 kHz

[TB = 30; 9.6 kHz

[TB = 20; 14.4 kHz

[TB = 15; 19.2 kHz

TX Counter B

RA Register

(5 bits)

RA’ Register

(6 bits)

(2’s compl)

Adder/

Subtractor

(6 bits)

Divide by 2

RB Register

(6 bits)

[RA = 9 (1)]

[RA = 18 (2)]

(6 bits)

RX Counter A

[RB = 40; 7.2 kHz

[RB = 36; 8.0 kHz

[RB = 30; 9.6 kHz

[RB = 20; 14.4 kHz

[RB = 15; 19.2 kHz

RX Counter B

Divide by 4

d0, d1 = 0,0

d0, d1 = 1,1‡

d0, d1 = 0,1

d0, d1 = 1,0‡

d0, d1 = 0,0

d0, d1 = 1,1‡

d0, d1 = 0,1

d0, d1 = 1,0‡

576-kHz

Pulses

576-kHz

Pulses

Low-Pass/

Switched

Capacitor Filter

CLK= 288-kHz

Square Wave

D/A

Conversion

Frequency

A/D

Conversion

Frequency

Band-Pass

Switched

Capacitor Filter

CLK= 288-kHz

Square Wave

SHIFT CLK

1.296 MHz (1)

2.592 MHz (2)

MSTR CLK

5.184 MHz (1)

10.368 MHz (2)

20.736 MHz (1)

41.472 MHz (2)

Optional External Circuitry

for Full-Duplex Modems

153.6 -kHz

Clock (1)

SCF Clock Frequency

+

Master Clock Frequency

2

Contents of Counter A

† Split-band filtering can alternatively be performed after the analog input function via software in the TMS320.

‡ These control bits are described in the AIC DX data word format section.

NOTE A: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for commercially available modem split-band filter clock), popular speech

and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as

submultiples of the crystal oscillator frequency. Since these derived frequencies sre synchronous submultiples of the crystal frequency,

aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.

Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital

signal processors.

Figure 1. Internal Timing Configuration