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TLC32040C Datasheet(PDF) 24 Page - Texas Instruments

Part # TLC32040C
Description  ANALOG INTERFACE CIRCUITS
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLC32040C Datasheet(HTML) 24 Page - Texas Instruments

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TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
serial port – AIC output signals
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
380
ns
tf(SCLK)
Shift clock (SCLK) fall time
50
ns
tr(SCLK)
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
45
55
%
td(CH-FL)
Delay from SCLK
↑ to FSR/FSX↓
CL = 50 pF
52
ns
td(CH-FH)
Delay from SCLK
↑ to FSR/FSX↑
CL = 50 pF
52
ns
td(CH-DR)
DR valid after SCLK
↑
90
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in word mode
90
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in word mode
90
ns
tf(EODX)
EODX fall time
15
ns
tf(EODR)
EODR fall time
15
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in byte mode
100
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in byte mode
100
ns
td(MH-SL)
Delay from MSTR CLK
↑ to SCLK↓
65
ns
td(MH-SH)
Delay from MSTR CLK
↑ to SCLK↑
65
ns
† Typical values are at TA = 25°C.



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