TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

20

POST OFFICE BOX 655303

total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High-level output voltage

VDD = 4.75 V, IOH = – 300 µA

2.4

V

VOL

Low-level output voltage

VDD = 4.75 V, IOL = 2 mA

0.4

V

ICC

Supply current from VCC

TLC3204_C

35

mA

ICC +

Supply current from VCC +

TLC3204_I

40

mA

ICC

Supply current from VCC

TLC3204_C

–35

mA

ICC –

Supply current from VCC –

TLC3204_I

–40

mA

IDD

Supply current from VDD

fMSTR CLK = 5.184 MHz

7

mA

Vref

Internal reference output voltage

3

3.3

V

∝Vref Temperature coefficient of internal reference voltage

200

ppm/

°C

ro

Output resistance at REF

100

k

Ω

receive amplifier input

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

A/D converter offset error (filters bypassed)

25

65

mV

A/D converter offset error (filters in)

25

65

mV

CMRR

Common-mode rejection ratio at IN +, IN –, or AUX IN +,

AUX IN –

See Note 6

55

dB

rl

Input resistance at IN +, IN –, or AUX IN +,AUX IN –, REF

100

k

Ω

transmit filter output

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOO

Output offset voltage at OUT +, OUT –, (single-ended

relative to ANLG GND)

15

75

mV

VOM

Maximum peak output voltage swing across RL at OUT +

or OUT –, (single ended)

RL ≥ 300 Ω, Offset voltage = 0

±3

V

VOM

Maximum peak output voltage swing between RL at OUT +

and OUT –, (differential output)

RL ≥ 600 Ω

±6

V

system distortion specifications, SCF clock frequency = 288 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Attenuation of second harmonic of A/D

Single ended

VI = – 0.5 dB to – 24 dB referred to Vref,

70

dB

input signal

Differential

Iref,

See Note 7

62

70

dB

Attenuation of third and higher harmonics

Single ended

VI = – 0.5 dB to – 24 dB referred to Vref,

65

dB

g

of A/D input signal

Differential

Iref,

See Note 7

57

65

dB

Attenuation of second harmonic of D/A

Single ended

VI = – 0 dB to – 24 dB referred to Vref,

70

dB

input signal

Differential

Iref,

See Note 7

62

70

dB

Attenuation of third and higher harmonics

Single ended

VI = – 0 dB to – 24 dB referred to Vref,

65

dB

g

of D/A input signal

Differential

Iref

See Note 7

57

65

dB

† All typical values are at TA = 25°C.

NOTES:

6. The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate.

7. The test condition VI is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC

is 600

Ω.