IPS2200 Datasheet

Jan.19.21

Page 25

A master can communicate with multiple slaves. Each slave device has an independent CSN line but shares the

SCK and SIO lines with all slaves. A slave is only addressed when the corresponding CSN pin is pulled low.

Chip Select #1

MCU

Data In/Out

Clock

DIO

SCK

SSN1

SSN2

Chip Select #2

IPS2200

#2

SIO_SDA

SCK_SCL

CSN_IRQN

IPS2200

#1

SIO_SDA

SCK_SCL

CSN_IRQN

VDD

4.7k

4.7k

Figure 17. Half Duplex 3-3 Wire SPI Multi-slave Interface

The SPI slave module is activated by the SPI 3-wire master, which initiates the transaction by pulling the chip-

select pin low (CSN_IRQN, pin 1). A serial clock (SCK_SCL, pin 15), is driven by the master. The Serial Data

In/Out line (SIO_SDA, pin 16) is a bidirectional data line between master and slave. In a typical scenario, the

master transmits a command with a specified length of 8-bit over the SIO line. If it is a write command, the

master keeps transmitting data over the same line. If the first bits were a READ command, the slave transmits a

fixed length of data over the SIO line to the master.

Table 19. SPI Interface Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

SPI clock rate

100

Kbit/s

Rise time of SIO

Signal level change from 10 to

90%; ≤15pF capacitive load

35

ns

Fall time of SDA or SCL

Signal level change from 90 to

10%;

≤15pF capacitive load

35

ns

Note: In Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20, for IPS2200 pins that have dual functions, the

function that is active is shown in bold font.

For a detailed description of the SPI interface, refer to the IPS2200 Programming Guide.

13.3

I2C Interface

The IPS2200 includes a standard I2C interface as the default interface. The I2C address is programmable. In

addition, the CSN_IRQN pin can be programmed as either an I2C address selection (SEL) pin or as an interrupt

output (IRQN) pin when using the I2C interface (see Table 3). The IPS2200 is configured as a I2C slave, several

slaves can be connected in parallel on the I2C bus.

Table 20. I2C Interface Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

I2C clock rate

100

Kbit/s

Low level state of SCL clock

4.7

µs

High level state of SCL clock

4.0

µs

Rise time of SDA or SCL

Signal level change from 10 to 90%

1000

ns

Fall time of SDA or SCL

Signal level change from 90 to 10%

300

ns