OPA375 datasheet(35/57 Pages) TI

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OPA375, OPA2375

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SBOS886C – NOVEMBER 2017 – REVISED JUNE 2020

Product Folder Links: OPA375 OPA2375

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10 Power Supply Recommendations

The OPA2375 and OPA4375 devices are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V). The

OPA375 device is specified for operation from 2.25 V to 5.5 V (±1.125 V to ±2.75 V). Many specifications of the

OPAx375 family apply from –40°C to 125°C.

CAUTION

Supply voltages larger than 7 V can permanently damage the device (see the Absolute

Maximum Ratings).

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout

Guidelines section.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational

amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than

crossing in parallel with the noisy trace.

•

Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in Figure 88.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

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