AT90PWM2 datasheet(136/365 Pages) ATMEL

136 / 365 page

136

AT90PWM2/3

4317A-3–AVR–02/05

Note:

1. See Figure 92 on page 165

Table 53. Block Inputs

Output Description

Table 54. Block Outputs

Table 55. Internal Outputs

Note:

1. See Figure 92 on page 165

2. See “Analog Synchronization” on page 164

CLK PLL

Clock Input from PLL

Signal

SYnIn

Synchronization In (from adjacent PSC)

(1)

Signal

StopIn

Stop Input (for synchronized mode)

Signal

Name

Description

Type/

Width

PSCINn

Input 0 used for Retrigger or Fault functions

Signal

from A C

Input 1 used for Retrigger or Fault functions

Signal

Name

Description

Type/

Width

Name

Description

Type/

Width

PSCOUTn0

PSC n Output 0 (from part A of PSC)

Signal

PSCOUTn1

PSC n Output 1 (from part B of PSC)

Signal

PSCOUTn2

(PSC2 only)

PSC n Output 2 (from part A or part B of PSC)

Signal

PSCOUTn3

(PSC2 only)

PSC n Output 3 (from part A or part B of PSC)

Signal

Name

Description

Type/

Width

SYnOut

Synchronization Output

(1)

Signal

PICRn

[11:0]

PSC n Input Capture Register

Counter value at retriggering event

12 bits

IRQPSCn

PSC Interrupt Request : three souces, overflow, fault,

and input capture

Signal

PSCnASY

ADC Synchronization (+ Amplifier Syncho. )

(2)

Signal

StopOut

Stop Output (for synchronized mode)

AT90PWM2 Datasheet(PDF) 136 Page - ATMEL Corporation

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