AT90PWM2 datasheet(193/365 Pages) ATMEL

193 / 365 page

193

AT90PWM2/3

4317B–AVR–02/05

Overview

A simplified block diagram of the USART Transmitter is shown in Figure 98. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

Figure 98. USART Block Diagram(1)

Note:

1. Refer to Pin Configurations3, Table 30 on page 75, and Table 28 on page 74 for

USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control registers are

shared by all units. The Clock Generation logic consists of synchronization logic for

external clock input used by synchronous slave operation, and the baud rate generator.

The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-

mitter consists of a single write buffer, a serial Shift Register, Parity Generator and

Control logic for handling different serial frame formats. The write buffer allows a contin-

uous transfer of data without any delay between frames. The Receiver is the most

complex part of the USART module due to its clock and data recovery units. The recov-

ery units are used for asynchronous data reception. In addition to the recovery units, the

Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The Receiver supports the same frame formats as the Transmit-

ter, and can detect Frame Error, Data OverRun and Parity Errors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA

UCSRB

UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxD

TxD

CONTROL

UDR

(Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

CLKio

SYNC LOGIC

Clock Generator

Transmitter

Receiver

AT90PWM2 Datasheet(PDF) 193 Page - ATMEL Corporation

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