AT90PWM2 datasheet(194/365 Pages) ATMEL

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194

AT90PWM2/3

4317B–AVR–02/05

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),

the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using synchronous mode.

Figure 99 shows a block diagram of the clock generation logic.

Figure 99. USART Clock Generation Logic, Block Diagram

Signal description:

txn clk Transmitter clock (Internal Signal).

rxn clk Receiver base clock (Internal Signal).

xn cki Input from XCK pin (internal Signal). Used for synchronous slave operation.

xn cko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fclk

System I/O Clock frequency.

Internal Clock Generation –

Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 99.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function

as a programmable prescaler or baud rate generator. The down-counter, running at sys-

tem clock (

fclk

io), is loaded with the UBRR value each time the counter has counted

down to zero or when the UBRRL Register is written. A clock is generated each time the

counter reaches zero. This clock is the baud rate generator clock output (=

fclk

io/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8

or 16 depending on mode. The baud rate generator output is used directly by the

Receiver’s clock and data recovery units. However, the recovery units use a state

machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL,

U2X and DDR_XCK bits.

Prescaling

Down-Counter

UBRRn

fclk

UBRRn+1

Sync

clk

XCKn

txn clk

U2Xn

UMSELn

DDR_XCKn

xn cki

xn cko

DDR_XCKn

rxn clk

Edge

Detector

UCPOLn

AT90PWM2 Datasheet(PDF) 194 Page - ATMEL Corporation

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