AT90PWM2 datasheet(212/365 Pages) ATMEL

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212

AT90PWM2/3

4317B–AVR–02/05

The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If

UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can

generate a Data Register Empty interrupt (see description of the UDRIE bit).

UDRE is set after a reset to indicate that the Transmitter is ready.

This bit is available in both USART and EUSART modes.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop

bit of received data is one. Always set this bit to zero when writing to UCSRA.

This bit is also valid in EUSART mode only when data bits are level encoded (in

Manchester mode the FEM bit allows to detect a framing error).

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the

receive buffer is full (two characters), it is a new character waiting in the Receive Shift

read. Always set this bit to zero when writing to UCSRA.

This bit is available in both USART and EUSART modes.

• Bit 2 – UPE: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

This bit is also valid in EUSART mode only when data bits are level encoded (there is no

parity in Manchester mode).

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling the transfer rate for asynchronous communication.

This bit is available in both USART and EUSART modes.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is writ-

ten to one, all the incoming frames received by the USART Receiver that do not contain

address information will be ignored. The Transmitter is unaffected by the MPCM setting.

For more detailed information see “Multi-processor Communication Mode” on page 209.

This mode is unavailable when the EUSART mode is set.

AT90PWM2 Datasheet(PDF) 212 Page - ATMEL Corporation