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AT90PWM2 Datasheet(PDF) 211 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 211 Page - ATMEL Corporation |
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211 / 365 page  211 AT90PWM2/3 4317B–AVR–02/05 USART Register Description USART I/O Data Register – UDR • Bit 7:0 – RxB7:0: Receive Data Buffer (read access) • Bit 7:0 – TxB7:0: Transmit Data Buffer (write access) The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXBn). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE flag in the UCSRA Register is set. Data written to UDR when the UDRE flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxDn pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. This register is available in both USART and EUSART modes. USART Control and Status Register A – UCSRA • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis- abled, the receive buffer will be flushed and consequently the RXC bit will become zero. The RXC flag can be used to generate a Receive Complete interrupt (see description of the RXCIE bit). This bit is available in both USART and EUSART modes. • Bit 6 – TXC: USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR). The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag can generate a Transmit Complete interrupt (see description of the TXCIE bit). This bit is available in both USART and EUSART modes. • Bit 5 – UDRE: USART Data Register Empty Bit 7 65432 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 RXC TXC UDRE FE DOR UPE U2X MPCM UCSRA Read/Write R R/W R R R R R/W R/W Initial Value 0 01 0000 0 |
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