AT90PWM2 datasheet(214/365 Pages) ATMEL

214 / 365 page

214

AT90PWM2/3

4317B–AVR–02/05

TXB8 is the ninth data bit in the character to be transmitted when operating with serial

frames with nine data bits. Must be written before writing the low bits to UDR.

When the EUSART mode is enable and configured in 17 bits transmit mode, this bit con-

tains the seventeenth bit (See EUSART section).

USART Control and Status

• Bit 7 – Reserved Bit

This bit is reserved for future use. For compatibilty with future devices, this bit must be

written to zero when USCRC is written.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

When configured in EUSART mode, the synchronous mode should not be set with

Manchester mode (See EUSART section).

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The Receiver will generate a parity value for the incoming data and com-

pare it to the UPM setting. If a mismatch is detected, the UPE Flag in UCSRA will be set.

This setting is available in EUSART mode only when data bits are level encoded (in

Manchester the parity checker and generator are not available).

Bit

765

432

UMSEL0

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

UCSRC

Read/Write

R/W

Initial Value

000

001

Table 78. UMSEL Bit Settings

UMSEL

Mode

Asynchronous Operation

Synchronous Operation

Table 79. UPM Bits Settings

UPM1

UPM0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

AT90PWM2 Datasheet(PDF) 214 Page - ATMEL Corporation

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