AT90PWM2 datasheet(215/365 Pages) ATMEL

215 / 365 page

215

AT90PWM2/3

4317B–AVR–02/05

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver

ignores this setting.

In EUSART mode, the USBS bit has the same behavior and the EUSB bit of the

EUSART allows to configure the number of stop bit for the receiver in this mode.

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

When the EUSART mode is set, these bits have no effect.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

Table 80. USBS Bit Settings

USBS

Stop Bit(s)

01-bit

12-bit

Table 81. UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

000

5-bit

001

6-bit

010

7-bit

011

8-bit

100

Reserved

101

Reserved

110

Reserved

111

9-bit

Table 82. UCPOL Bit Settings

UCPOL

Transmitted Data Changed

(Output of TxDn Pin)

Received Data Sampled

(Input on RxD Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

AT90PWM2 Datasheet(PDF) 215 Page - ATMEL Corporation

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