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EMC1702 Datasheet(PDF) 50 Page - Microchip Technology |
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EMC1702 Datasheet(HTML) 50 Page - Microchip Technology |
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50 / 60 page ![]() EMC1702 DS20006455A 50 2020 Microchip Technology Inc. The Source Voltage registers store the voltage measured at the SENSE+ pin (see Section 4.1.2, "Voltage Measurement") as a digital value, VSOURCE, consisting of a high byte and low byte with five of its LSBs always zero. The measured voltage is determined by summing the bit weights of each bit set. For example, if VBUS was 7.4V, the Source Voltage registers would read 0100_1110 for the high byte and 1100_0000b for the low byte corresponding to 6V + 0.75V + 0.375V + 0.1875V + 0.0469V + 0.0234V = 7.383V. The bit weightings are assigned for human interpretation. They should be disregarded when translating the information via a computing system as shown in Section 4.1.2, "Voltage Measurement". The Source Voltage registers cannot support negative values, and all values less than 0V will be recorded as 0V. 5.24 Power Ratio Registers The Power Ratio registers store a power factor value that is used to determine the final average power delivered to the system (see Section 4.1.3, "Power Calculation"). The power factor value is the result of the multiplication of the VSENSE reading and the VSOURCE reading values shifted to a 16-bit number. It represents the ratio of delivered power with respect to maximum power. 5.25 VSENSE Limit Registers The VSENSE Limit registers store a high and low limit for VSENSE. VSENSE is compared against both limits after each update. The data format for the limit is a raw binary form that is relative to the maximum VSENSE that has been programmed. If the measured sense voltage meets or exceeds the high limit or drops below the low limit, the ALERT pin is asserted and the VSENSE_HIGH or VSENSE_LOW status bits are set in the High Limit Status or Low Limit Status registers (see Section 5.15 and Section 5.16). APPLICATION NOTE: VSENSE is always checked to be greater than the high limit or less than the low limit including when VSENSE is negative. Table 5.39 Power Ratio Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 5Bh R Power Ratio High Byte 32768 16384 8192 4096 2048 1024 512 256 00h 5Ch R Power Ratio Low Byte 128 64 32 16 8 4 2 1 00h Table 5.40 VSENSE Limit Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 60h R/W Sense Voltage High Limit Sign 1024 512 256 128 64 32 16 7Fh 61h R/W Sense Voltage Low Limit Sign 1024 512 256 128 64 32 16 80h |
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