NXP Semiconductors

46

CD1020

The fault/status diagnostic capability consists of one internal 24-bit register. The content of the fault/status register is shown in Table 38.

Bits 0 – 21 show the status of each input where logic [1] is a closed switch and logic [0] is an open switch. In addition to input status

information, fault status such as die over-temp, Hash fault, SPI errors, as well as interrupts are reported.

A SPI read cycle is initiated by a CS_B logic ‘1’ to ‘0’ transition, followed by 32 SCLK cycles to shift the fault/status registers out the MISO

pin. The INT_B pin is cleared 1.0 ms after the falling edge of CS_B. The fault is immediately set again if the fault condition is still present.

The Fault Status bit sets any time a Fault occurs, and the Fault register (Table 39) must be read in order to clear the Fault status flag.

The intflg bit sets anytime an interrupt event occurs (change of state on switch, any fault status bit gets set). Any SPI message that will

return intflg bit will clear this flag, even if the event is still occurring. For example an overtemp, will cause an interrupt. The interrupt can

be cleared but the chip will not interrupt again, based on the overtemp until that fault has gone away.

Bit 23 : Fault Status:

• 0 = No Fault

• 1 = Indicates a fault has occurred and should be viewed in the fault status register.

Bit 22 : Intflg:

• 0 = No Change of state

• 1 = Change of state detected.

Bit 21 – 0 : SPx /SGx input status:

• 0 = Open switch

• 1 = Closed switch

Table 37. Read switch status command

Register address

R

SPI data bits [23 – 0]

[31–25]

[24]

bit 23

bit 22

bit 21

bit 20

bit 19

bit 18

bit 17

bit 16

0011_111

0

FAULT

STATUS

INTflg

SP7

SP6

SP5

SP4

SP3

SP2

Default After POR

1

1

XXX

XXX

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

SP1

SP0

SG13

SG12

SG11

SG10

SG9

SG8

X

XXXX

XXX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SG7SG6

SG5SG4

SG3SG2

SG1SG0

X

XXXX

XXX

MISO return word

bit [23]

bit [22]

bits [21–14]

bits [13–0]

0011_1110

FAULT

STATUS

INTflg

SP7 –SP0 Switch Status

SG13 – SG0 Switch Status

Table 38. MISO output register definition

MISO

Response

Sends