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CD1020 Datasheet(PDF) 12 Page - NXP Semiconductors

Part # CD1020
Description  22 channel multiple switch detection interface
PDF  56 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CD1020 Datasheet(HTML) 12 Page - NXP Semiconductors

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NXP Semiconductors
12
CD1020
4.4.2
Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics
TA = –40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a
100 pF load on MISO, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Units
Notes
General
tACTIVE
POR to active time
• Undervoltage to normal mode
250
340
450
µs
Switch input
tPULSE(ON)
Pulse wetting current timer
• Normal mode
17
20
23
ms
tINT-DLY
Interrupt delay time
• Normal mode
——
18.5
µs
tPOLLING_TIMER
Polling timer accuracy
• Low-power mode
——
15
%
tACTIVEPOLLSGTIME Tactivepoll timer SG
49.5
58
66.5
µs
tACTIVEPOLLSBTIME
Tactivepoll timer SB
• SBPOLLTIME = 0
• SBPOLLTIME = 1
1.0
49.5
1.2
58
1.4
66.5
ms
µs
tGLITCHTIMER
Input glitch filter timer
• Normal mode
5.0
—
18
µs
AMUX output
AMUXVALID
AMUX access time (selected output to selected output)
• CMUX = 1.0 nF, Rising edge of CS_B to selected
—
(22)
—
μs
AMUXVALIDTS
AMUX access time (tri-state to ON)
• CMUX = 1.0 nF, rising edge of CS_B to selected
——
20
μs
Oscillator
OSCTOLLPM
Oscillator tolerance at 192 kHz in low-power mode
–15
—
15
%
OSCTOLNOR
Oscillator tolerance normal mode at 4.0 MHz
–15
—
15
%
Interrupt
INTPULSE
INT pulse duration
• Interrupt occurs or INT_B request
90
100
110
µs
SPI interface
fOP
Transfer frequency
—
—
8.0
MHz
tSCK
SCLK period
• Figure 6 - 1
160
—
—
ns
tLEAD
Enable lead time
• Figure 6 - 2
140
—
—
ns
tLAG
Enable lag time
• Figure 6 - 3
50
—
—
ns
tSCKHS
SCLK high time
• Figure 6 - 4
56
—
—
ns



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