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Z8932320FSC Datasheet(PDF) 23 Page - Zilog, Inc. |
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Z8932320FSC Datasheet(HTML) 23 Page - Zilog, Inc. |
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23 / 60 page ![]() Z89223/273/323/373 ZiLOG 16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 23 Figure 15. SPI Timing (Master and Slave Modes) SDI-SCLK Setup SCLK-SDI Hold SS-SDO Valid SS-SCLK Setup Valid Valid SCLK* SDO SS* SDI SCLK-SDO Valid TRI-STATE *Notes: The polarity of SCLK and SS are programmable by the user. SS is used in Slave Mode only. This figure illustrates data transmission on the falling edge of SCLK, data reception on the rising edge of SCLK, with SS active Low (default). |
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