Z8932320FSC datasheet(43/60 Pages) ZILOG

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ZiLOG

16-Bit Digital Signal Processors with A/D Converter

DS000202-DSP0599

GENERAL-PURPOSE COUNTER/TIMER (C/T2)

This versatile16-bit C/T offers multiple uses, including

Sleep Mode Wake-up. It can be clocked with the slow

32 kHz crystal clock (CLKI), while the DSP and other pe-

ripheral functions operate at a higher frequency generated

by the PLL. Also included is an independent long duration

timer.

GPT is a 16-bit down counter that holds the current C/T val-

ue. It can be read like any other ordinary register. GPTL and

GPT share the same address, Bank14/EXT0. A write to

GPTL reloads GPT, causing the C/T to be retriggered.

When C/T2 underflows, it is reloaded with the most recent

value written to GPTL. If the C/T2 interrupt is enabled, at

underflow an interrupt is generated. The counting operation

of the counter can be disabled. The C/T clock source can

be selected to be CLKI, UI2, or the system clock divided

by 2. When the C/T2 output is enabled, it drives the TMO2

pin.

Bank 15/EXT2 is the control register for C/T2, and for I/O

Ports 2 and 3. Refer to the I/O Ports section, page 33, for a

description of the I/O port bit allocation.

Table 22. C/T2 Bits D15 and D13

D15

D13

C/T2 Clock

Sleep/Wake-Up

Mode

SYSCLK ÷ 2

(default)

n/a

UI2

n/a

CLKI

Disabled

CLKI

Enabled

Figure 37. Counter/Timer2 Block Diagram

TMR

TMO2

Sleep Mode

Wake-Up

Timer Load Register

16-Bit Down Counter

GPT–Bank14/EXT0 (Read)

GPTL–Bank14/EXT0 Write

System Clock

UI2

CLKI

MUX

÷2

MUX

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