Z8932320FSC datasheet(36/60 Pages) ZILOG

36 / 60 page

Z89223/273/323/373

16-Bit Digital Signal Processors with A/D Converter

ZiLOG

DS000202-DSP0599

I/O PORTS (Continued)

Port2Ñ8-Bit Programmable I/O

Bank15/EXT2 is the Port2 control register. The LSB is the

Port2 direction control. Port2 data is accessed as the MSB

of EXT5 in Banks 0,1,or 5. The Port2 pins can also be

mapped to internal functions. When INT0, INT1, TMO0,

TMO1, WAIT, UI2, or TMO2 are enabled, they use Port2

pins. The 44-pin packages do not feature Port2 pins

P2.7–P2.5.

Table 17. Port2 Bit Function Allocation

Port Pin

Condition

Then

Else

P2.0/INT0

Bank15/EXT2 Bit 9 = 1

Enable INT0

INT0

P2.0

P2.1/INT1

Bank15/EXT1 Bit 4 = 1

Enable INT1

INT1

P2.1

P2.2/TMO0

Bank13/EXT1 Bit [6,5] = 10, or

Bank14/EXT1 Bit [6,5] = 10

Enable TMO0

TMO0

P2.2

P2.3/TMO1

Bank13/EXT1 Bit [6,5] = 11, or

Bank14/EXT1 Bit [6,5] = 11

Enable TMO1

TMO1

P2.3

P2.4/WAIT

Bank15/EXT3 Bit 14 = 1

Enable WAIT

WAIT

P2.4

P2.5/UI2

Bank15/EXT2 Bit 13 = 1

C/T2 clock is UI2

UI2

P2.5

P2.6/TMO2

Bank15/EXT2 Bits 14 = 1

Enable TMO2

TMO2

P2.6

P2.7

Figure 27. Bank15/EXT2 Register

D7 D6

D5 D4 D3

D2 D1

D15 D14 D13 D12 D11 D10 D9

Bank 15/EXT2

Port2 I/O Directions

0 = Input (default)

1 = Output

Port3

0 = Disabled (default)

1 = Enabled

INT0

0 = Disabled (default)

1 = Enabled

Port2 Outputs

0 = Push-Pull (default)

1 = Open-Drain

Counter/Timer2

0 = Disabled (default)

1 = Enabled

Counter/Timer2 Operation

0 = Stopped (default)

1 = Counting

If D15 = 0, Counter/Timer2 Clock defined by

0 = System Clock/2 (default)

1 = UI2

If D15 = 1, Counter/Timer2 Sleep Mode Wake-Up

0 = Disabled (default)

1 = Enabled

TMO2

Counter/Timer2 Clock

0 = Disabled (default)

1 = Enabled

0 = Defined by D13 (default)

1 = CLKI

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