Z8932320FSC datasheet(32/60 Pages) ZILOG

32 / 60 page

Z89223/273/323/373

16-Bit Digital Signal Processors with A/D Converter

ZiLOG

DS000202-DSP0599

BANK/EXT REGISTER ASSIGNMENTS (Continued)

Interrupt Polarity RegisterÑBank14/EXT6

The trigger polarities, rising-edge or falling-edge, of all the

external interrupts are programmable.

Wait-State Control RegisterÑBank15/EXT3

The Wait-State Control Register enables the insertion of

wait states when the DSP accesses slow peripherals. This

bus, providing 100 ns of access time instead of 50 ns when

operating at 20 MHz. When more than one wait state is nec-

essary, input pin P2.4/ WAIT can be used to provide addi-

tional wait states. The Wait-State Register enables the user

to specify which EXT registers, EXT0–EXT6, and which

operation, read and/or write, require a wait state. EXT7 is

an internal register, and requires no wait state.

Figure 22. Interrupt Polarity Register

D1 D0

D15 D14 D13 D12 D11 D10

Bank 14/Ext 6 Reg

INT0 Polarity

0 : Rising Edge (default)

1 : Falling Edge

INT1 Polarity

0 : Rising Edge (default)

1 : Falling Edge

INT2 Polarity

0 : Rising Edge (default)

1 : Falling Edge

Bits [15:3]—Reserved

Figure 23. Wait-State Control Register

D15 D14 D13 D12 D11 D10

Bank15/EXT3 Reg

Wait-State EXT6

Wait-State EXT0

Bit14: 0 = Disabled WAIT Input Pin (default)

1 = Enabled P2.4 as WAIT Input Pin

Bit 15: 0 = Disabled UO0, UO1 (default)

1 = Enable UO0, UO1

Wait-State EXT5

Wait-State EXT4

Wait-State EXT3

Wait-State EXT2

Wait-State EXT1

00 = read (nws), write (nws)

01 = read (nws), write (nws)

10 = read (ws), write (ws)

11 = read (ws), write (ws)

nws = no wait state

ws = one wait state

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