Z8932320FSC datasheet(40/60 Pages) ZILOG

40 / 60 page

Z89223/273/323/373

16-Bit Digital Signal Processors with A/D Converter

ZiLOG

DS000202-DSP0599

PERIPHERALS (Continued)

Counter/Timers (C/T0 and C/T1)

The Z893x3 features two 16-bit Counter/Timers (C/T) that

can be independently configured to operate in various

modes. Each is implemented as a 16-bit Load Register and

a 16-bit down counter. Either C/T input can be selected from

UI0 or UI1. Either C/T output can be directed to TMO0 or

TMO1. The C/T clock is a scaled version of the system

clock. Each C/T features an 8-bit prescaler. The clock rates

of the two C/T are independent of each other. The C/Ts can

be programmed to recognize clock events on the rising

edge, the falling edge, or both rising and falling edges of

the input signal. Outputs on TMO0 or TMO1 can be pro-

grammed to occur with either polarity.

If either C/T is enabled and an output pin TMO0 or TMO1

is selected, and at the same time User Outputs are enabled,

the C/T takes precedence, and Status Register bits 5 or 6

do not affect the state of the selected pin.

C/T Modes of Operation:

MODE 0—Square Wave Output.

The C/T is configured

to generate a continuous square wave of 50% duty cycle.

Writing a new value to the TMLR Register takes effect at

the end of the current cycle, unless TMR is written.

MODE 1—Retriggerable One-Shot.

The C/T is config-

ured to generate a single pulse of programmable duration.

The pulse may be either logic High or logic Low. Retrig-

gering the one-shot before the end of the pulse causes it to

retrigger for a new duration.

MODE 2—8-Bit PWM.

The C/T is configured to generate

a pulse-width modulated waveform. The duty cycle ranges

from 0–100% (0/256 to 255/256; 8-bits) of a cycle in steps

of 1/256 of a cycle. The asserted state of the waveform may

be either logic High or logic Low. Writing a new pulse-

width value to the TMLR Register takes effect at the end

of current cycle, unless TMR is written.

MODE 3—16-Bit PWM.

The C/T is configured to generate

a pulse-width modulated waveform. The duty cycle ranges

from 0–100% (0/65,536 to 65,535/65,536; 16-bits) of a cy-

cle in steps of 1/65,536 of a cycle. The asserted state of the

waveform may be either logic High or logic Low. Writing

a new pulse-width value to the TMLR Register takes effect

at the end of current cycle, unless TMR is written.

MODE 4—Finite Pulse String Generator.

The C/T is

configured to generate 1 to 65,535 pulses. The output pulses

are actually from the Timer Clock Prescaler divided by 2

(TMCLK). They are gated to the output until the Timer

Down-Counter underflows.

MODE 5—Externally Clocked One-Shot.

The C/T is

configured to generate an output pulse. The pulse may be

either logic High or logic Low. It is deasserted when a pro-

grammable number of input events (up to 65,535) occur on

the input pin, UI0 or UI1.

MODE 6—Software Watch-Dog Timer.

The C/T is con-

figured to generate a Hardware Reset on time-out, unless

retriggered by software.

MODE 7—Hardware Watch-Dog Timer.

The C/T is con-

figured to generate a Hardware Reset on time-out unless re-

triggered by an event on the input pin, UI0 or UI1.

MODE 8—Pulse Stopwatch.

The C/T is configured to

measure the time during which its input is asserted.

MODE 9—Edge-to-Edge Stopwatch.

The C/T is config-

ured to measure the period from one rising (falling) edge

to the next rising (falling) edge on the input.

MODE 10—Edge Counter.

The C/T is configured to count

a number of input edges (up to 65,535). Input edges may

be selected as rising or falling or both.

MODE 11—Gated Edge Counter.

The C/T is configured

to count the number of input edges (up to 65,535) in a time

window set by the second timer. Edges are counted until the

second timer underflows. Input edges may be selected as

rising, falling, or both.

Figure 31. Counter/Timer 0 and 1 Block Diagram

8 7

UI1 UI0

TPLR

TMLR

TMR

TPR

Timer Load Register

16-Bit Down Counter

TMCLKOUT =

TMCLK

(TMR + 1)

TMCLKIN =

System Clock

8-Bit Counter

Prescaler Value

Zeros

80h

÷2

MUX

2 x (TPR + 1)

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