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Z8932320FSC Datasheet(PDF) 52 Page - Zilog, Inc.

Part # Z8932320FSC
Description  16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER
PDF  60 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8932320FSC Datasheet(HTML) 52 Page - Zilog, Inc.

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Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
52
DS000202-DSP0599
INSTRUCTION DESCRIPTIONS (Continued)
LD
Load
destination
with source
LD<dest>,<src>
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memind>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<simm>
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memind>
<hwregs>,<regind>
<hwregs>,<hwregs>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
2
3
3
1
1
LD A,X
LD A,D0:0
LD A,P0:1
LD A,@P1:1
LD A,@D0:0
LD A,124
LD 124,A
LD D0:0,EXT7
LD P1:1,#%FA
LD P1:1,EXT1
LD@P1:1,#1234
LD @P1:1+,X
LD Y,P0:0
LD SR,D0:0
LD PC,#%1234
LD X,@A
LD Y,@D0:0
LD A,@P0:0–LOOP
LD X,EXT6
Notes:
When <dest> is <hwregs>, <dest> cannot be P.
When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn if <src> is EXTn,
<dest> cannot be X if <src> is X, <dest> cannot be SR if <src> is SR.
When <src> is <accind> <dest> cannot be A.
MLD
Multiply
MLD <src1>,<src2>
[,<bank switch>]
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
1
1
1
1
1
1
1
1
MLD A,@P0:0+LOOP
MLD A,@P1:0,OFF
MLD @P1:1,@P2:0
MLD @P0:1,@P1:0,ON
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands
<regind>, the <bank switch> defaults to ON.
MPYA
Multiply and
add
MPYA <src1>,<src2>
[,<bank switch>]
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
1
1
1
1
1
1
1
1
MPYA A,@P0:0
MPYA A,@P1:0,OFF
MPYA @P1:1,@P2:0
MPYA@P0:1,@P1:0,ON
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank
switch> defaults to ON.
MPYS
Multiply and
subtract
MPYS <src1>,<src2>
[,<bank switch>]
<hwregs>,<regind>
<hwregs>,<regind>,
<bank switch>
<regind>,<regind>
<regind>,<regind>,
<bank switch>
1
1
1
1
1
1
1
1
MPYS A,@P0:0
MPYS A,@P1:0,OFF
MPYS @P1:1,@P2:0
MPYS
@P0:1,@P1:0,ON
Inst.
Description
Synopsis
Operands
Words
Cycles Examples



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