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Z8932320FSC Datasheet(PDF) 53 Page - Zilog, Inc.

Part # Z8932320FSC
Description  16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER
PDF  60 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8932320FSC Datasheet(HTML) 53 Page - Zilog, Inc.

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Z89223/273/323/373
ZiLOG
16-Bit Digital Signal Processors with A/D Converter
DS000202-DSP0599
53
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind>
the <bank switch> defaults to ON.
NEG
Negate
NEG <cc>,A
<cc>, A
A
1
1
1
1
NEG MI,A
NEG A
NOP
No operation NOP
None
1
1
NOP
OR
Bitwise OR
OR <dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
1
2
3
1
1
1
1
OR A,P0:1
OR A, D0:1
OR A,#%2C21
OR A,@@P2:1+
OR A, %2C
OR A,@P1:0–LOOP
OR A,EXT6
OR A,#%12
POP
Pop value
from stack
POP <dest>
<pregs>
<dregs>
<regind>
<hwregs>
1
1
1
1
1
1
1
1
POP P0:0
POP D0:1
POP @P0:0
POP A
PUSH
Push value
onto stack
PUSH <src>
<pregs>
<dregs>
<regind>
<hwregs>
<limm>
<accind>
<memind>
1
1
1
1
2
1
1
1
1
1
1
2
3
3
PUSH P0:0
PUSH D0:1
PUSH @P0:0
PUSH BUS
PUSH #12345
PUSH @A
PUSH @@P0:0
RET
Return from
subroutine
RET
None
1
2
RET
RL
Rotate Left
RL <cc>,A
<cc>,A
A
1
1
1
1
RL NZ,A
RL A
RR
Rotate Right
RR <cc>,A
<cc>,A
A
1
1
1
1
RR C,A
RR A
SCF
Set C flag
SCF
None
1
1
SCF
SIEF
Set IE flag
SIEF
None
1
1
SIEF
SLL
Shift left
logical
SLL
[<cc>,]A
A
1
1
1
1
SLL NZ,A
SLL A
SOPF
Set OP flag
SOPF
None
1
1
SOPF
SRA
Shift right
arithmetic
SRA<cc>,A
<cc>,A
A
1
1
1
1
SRA NZ,A
SRA A
SUB
Subtract
SUB<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
1
2
3
1
1
1
1
SUB A,P1:1
SUB A,D0:1
SUB A,#%2C2C
SUB A,@D0:1
SUB A,%15
SUB A,@P2:0–LOOP
SUB A,STACK
SUB A, #%12
Inst.
Description
Synopsis
Operands
Words
Cycles Examples



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