AD4116 datasheet(40/59 Pages) AD

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AD4116

Data Sheet

Rev. 0 | Page 40 of 59

DIGITAL INTERFACE

The programmable functions of the AD4116 are accessible via

the SPI. The SPI of the AD4116 consists of four signals: CS,

DIN, SCLK, and DOUT/RDY. The DIN line transfers data into

the on-chip registers. The DOUT output accesses data from the

on-chip registers. SCLK is the serial clock input for the device. All

data transfers (either on DIN or on DOUT) occur with respect to

the SCLK signal.

The DOUT/RDY pin also functions as a data ready signal, with

the line going low if CS is low when a new data-word is available

in the data register. The DOUT/RDY pin is reset high when a

read operation from the data register is complete. The RDY

output also goes high before updating the data register to

indicate when not to read from the device to ensure that a data

read is not attempted while the register is being updated. Take

care to avoid reading from the data register when RDY is about

to go low. The best method to ensure that no data read occurs is to

always monitor the RDY output. Start reading the data register

as soon as RDY goes low, and ensure a sufficient SCLK rate,

such that the read is completed before the next conversion result.

CS is used to select a device. CS can be used to decode the

AD4116 in systems where several components are connected to

the serial bus.

Figure 2 and Figure 3 show timing diagrams for interfacing to

the AD4116 using CS to decode the device. Figure 2 shows the

timing for a read operation from the AD4116, and Figure 3

shows the timing for a write operation to the AD4116. It is

possible to read from the data register several times, even though

the RDY output returns high after the first read operation.

However, take care to ensure that the read operations are

completed before the next output update occurs. In continuous

read mode, the data register can be read only once.

The serial interface can operate in 3-wire mode by tying CS

low. In this case, the SCLK, DIN, and DOUT/RDY lines are

used to communicate with the AD4116. The end of the

conversion can also be monitored using the RDY bit in the

status register.

The SPI can be reset by writing 64 SCLKs with CS = 0 and

DIN = 1. A reset returns the SPI to the state in which it expects a

write to the communications register. This operation resets the

contents of all registers to their power-on values. Following a

reset, allow a period of 500 µs before addressing the SPI.

CHECKSUM PROTECTION

The AD4116 has a checksum mode that can improve interface

robustness. Using the checksum mode ensures that only valid

data is written to a register and allows data read from a register

to be validated. If an error occurs during a register write, the

CRC_ERROR bit is set in the status register. However, to

ensure that the register write is completed. It is important to

read back the register and verify the checksum.

For CRC checksum calculations during a write operation, the

following polynomial is always used:

x8 + x2 + x + 1

During read operations, the user can select between this

polynomial and a similar exclusive OR (XOR) function. The

XOR function requires less time to process on the host

microcontroller than the polynomial-based checksum. The

CRC_EN bits in the interface mode register enable and disable

the checksum and allow the user to select between the polynomial

check and the simple XOR check.

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to 24-bit

data. For a read transaction, the checksum is calculated using

the command word and the 8-bit to 32-bit data output. Figure 60

and Figure 61 show SPI write and read transactions, respectively.

8-BIT COMMAND

8-BIT CRC

UP TO 24-BIT INPUT

CMD

DATA

CRC

DIN

SCLK

Figure 60. SPI Write Transaction with CRC

8-BIT COMMAND

8-BIT CRC

UP TO 32-BIT

OUTPUT

CMD

DATA

CRC

DIN

SCLK

DOUT/

RDY

Figure 61. SPI Read Transaction with CRC

If checksum protection is enabled when continuous read mode

is active, there is an implied read data command of 0x44 before

every data transmission that must be accounted for when

calculating the checksum value. The checksum protection ensures

a nonzero checksum value even if the ADC data equals 0x000000.

AD4116 Datasheet(PDF) 40 Page - Analog Devices

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