AD4116 datasheet(30/59 Pages) AD

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AD4116

Data Sheet

Rev. 0 | Page 30 of 59

2.5V VREF

0.1µF

ADR45252

3V TO 18V

0.1µF

4.7µF

AD4116

REF+

REF–

1 ALL DECOUPLING IS TO AVSS.

2 ANY OF THE ADR452x FAMILY REFERENCES CAN BE USED.

ADR4525 ENABLES REUSE OF THE 5V ANALOG SUPPLY

NEEDED FOR AVDD TO POWER THE REFERENCE VIN.

Figure 42. ADR4525 Connected to AD4116 REF± Pins

Table 20. Setup Configuration 0 Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x20

SETUPCON0

[15:8]

Reserved

BI_UNIPOLAR0

REFBUF0+

REFBUF0−

INBUF0

0x1000

[7:0]

Reserved

REF_SEL0

Reserved

Table 21. ADC Mode Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x01

ADCMODE

[15:8]

REF_EN

Reserved

SING_CYC

Reserved

Delay

0x2000

[7:0]

Reserved

Mode

CLOCKSEL

Reserved

BUFFERED REFERENCE INPUT

The AD4116 has true rail-to-rail, integrated, precision unity

gain buffers on both ADC reference inputs. The buffers provide

the benefit of providing high input impedance and allowing

high impedance external sources to be directly connected to the

reference inputs. The integrated reference buffers can fully

drive the internal reference switch capacitor sampling network,

simplifying the reference circuit requirements. Each reference

input buffer amplifier is fully chopped, meaning that it minimizes

the offset error drift and 1/f noise of the buffer. When using a

reference, such as the ADR4525, these buffers are not required

because these references, with proper decoupling, can drive the

reference inputs directly.

CLOCK SOURCE

The AD4116 uses a nominal master clock of 4 MHz. The AD4116

can source its sampling clock from one of three sources:

•

An internal oscillator

•

An external crystal (use a 16 MHz crystal automatically

divided internally to set the 4 MHz clock)

•

An external clock source

All output data rates listed in this data sheet relate to a master

clock rate of 4 MHz. Using a lower clock frequency from, for

instance, an external source scales any listed data rate

proportionally. To achieve the specified data rates, particularly

rates for rejection of 50 Hz and 60 Hz, use a 4 MHz clock. The

source of the master clock is selected by setting the CLOCKSEL bits

(Bits[3:2]) in the ADC mode register. The default operation on

power-up and reset of the AD4116 is to operate with the internal

oscillator. It is possible to fine tune the output data rate and

filter notch at low output data rates using the SINC3_MAPx bits.

Internal Oscillator

The internal oscillator runs at 16 MHz and is internally divided

down to 4 MHz for the modulator and can be used as the ADC

master clock. The internal oscillator is the default clock source for

the AD4116 and is specified with an accuracy of −2.5% to +2.5%.

There is an option to allow the internal clock oscillator to be output

on the XTAL2/CLKIO pin. The clock output is driven to the

IOVDD logic level. This option can affect the dc performance of

the AD4116 due to the disturbance introduced by the output

driver. The extent to which the performance is affected depends

on the IOVDD voltage supply. Higher IOVDD voltages create a

wider logic output swing from the driver and affect performance

to a greater extent. This effect is further exaggerated if the

IOSTRENGTH bit is set at higher IOVDD levels.

AD4116 Datasheet(PDF) 30 Page - Analog Devices

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