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AD4116 Datasheet(PDF) 18 Page - Analog Devices

Part # AD4116
Description  Single Supply, 24-Bit, Sigma-Delta ADC with 짹10 V, 10 M廓 Inputs and Buffered Low Level Inputs
PDF  59 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4116 Datasheet(HTML) 18 Page - Analog Devices

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AD4116
Data Sheet
Rev. 0 | Page 18 of 59
NOISE PERFORMANCE AND RESOLUTION
Table 7 to Table 10 show the rms noise, peak-to-peak noise,
effective resolution, and the noise free (peak-to-peak)
resolution of the AD4116 for various ODRs. These values are
typical and are measured with an external 2.5 V reference,
analog input buffers enabled and with the ADC continuously
converting on multiple channels. The values in Table 7 and
Table 8 are generated for the ±10 V voltage input range, with a
differential input voltage of 0 V. The values in Table 9 and
Table 10 are generated for the ±VREF input range, with a
differential input voltage of 0 V. It is important to note that the
peak-to-peak resolution is calculated based on the peak-to-peak
noise. The peak-to-peak resolution represents the resolution for
which there is no code flicker.
Table 7. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter
Default ODR (SPS);
SING_CYC = 0 and
Single Channel Enabled
ODR (SPS per Channel);
SING_CYC = 1 or Multiple
Channels Enabled
Settling
Time1
Notch
Frequency
(Hz)
Noise
(μV rms)2
Effective
Resolution
(Bits)
Noise
(μV p-p)
Peak-to-Peak
Resolution
(Bits)
62,500
12,422.36
80.5 μs
62,500
326.60
15.90
2038.60
13.26
31,250
10,362.69
96.5 μs
31,250
271.80
16.17
1778.01
13.46
15,625
7,782.1
128.5 μs
15,625
209.60
16.54
1360.18
13.84
10,416.7
6,230.53
160.5 μs
10,416.7
171.80
16.83
1093.80
14.16
5,194.8
5,194.8
192.5 μs
7,812.5
151.40
17.01
1006.20
14.28
2,496.9
2,496.9
400.5 μs
2,976.19
95.46
17.68
585.80
15.06
1007.6
1007.6
992.50 μs
1077.59
56.48
18.43
373.60
15.71
499.9
499.9
2.00 ms
516.53
39.56
18.95
247.80
16.30
390.6
390.6
2.56 ms
400.64
35.82
19.09
235.80
16.37
200.3
200.3
4.99 ms
202.92
25.72
19.57
163.40
16.90
100.0
100.0
10.00 ms
100.6
19.08
20.00
116.00
17.40
59.75
59.75
16.74 ms
59.98
15.22
20.33
98.16
17.64
49.84
49.84
20.06 ms
50
14.07
20.44
76.89
17.99
20.00
20.00
50.00 ms
20.03
10.32
20.89
51.85
18.56
16.65
16.65
60.06 ms
16.67
9.62
20.99
50.66
18.59
10.00
10.00
100.00 ms
10.01
8.67
21.14
42.32
18.85
5.00
5.00
200.00 ms
5
7.78
21.29
38.74
18.98
2.50
2.50
400.00 ms
2.5
6.52
21.55
32.78
19.22
1.25
1.25
800.00 ms
1.25
6.23
21.61
31.59
19.27
1 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 Based on 1000 samples for data rates ≥ 59.75 SPS per channel, and based on 100 samples for data rates ≤ 49.84 SPS per channel.
Table 8. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter
Default ODR (SPS);
SING_CYC = 0 and
Single Channel Enabled
ODR (SPS per Channel);
SING_CYC = 1 or
Multiple Channels Enabled
Settling
Time1
Notch
Frequency
(Hz)
Noise
(μV rms)2
Effective
Resolution
(Bits)
Noise
(μV p-p)
Peak-to-Peak
Resolution
(Bits)
62,500
20,618.56
48.5 μs
62,500
1213.00
14.01
7641.80
11.35
31,250
10,362.69
96.5 μs
31,250
279.20
16.13
1748.20
13.49
15,625
5,194.81
192.5 μs
15,625
163.40
16.90
1031.76
14.24
10,416.7
3,466.2
288.5 μs
10,416.7
133.38
17.19
891.69
14.46
5,208.3
1,734.61
576.5 μs
5,208.3
95.20
17.68
608.60
15.01
2,500
832.99
1.20 ms
2,500
64.90
18.23
435.00
15.49
1008.1
335.97
2.98 ms
1008.1
41.82
18.87
260.80
16.23
500
166.65
6.00 ms
500
30.12
19.34
205.40
16.57
400.64
133.54
7.49 ms
400.64
27.68
19.46
179.60
16.77
200.32
66.77
14.98 ms
200.32
20.22
19.92
140.00
17.12
100.0
33.3
30.00 ms
100.0
15.30
20.32
96.46
17.67
59.98
19.99
50.02 ms
59.98
12.88
20.57
87.62
17.81
50
16.67
60.00 ms
50.00
12.40
20.62
60.79
18.34
20
6.67
150.00 ms
20.00
8.64
21.14
42.91
18.83
16.67
5.56
180.00 ms
16.67
8.34
21.20
42.91
18.79



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