AD4116 datasheet(11/59 Pages) AD

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Data Sheet

AD4116

Rev. 0 | Page 11 of 59

Pin No.

Mnemonic1

Type2

Description

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register

identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt

triggered input.

Chip Select Input. The CS pin is an active low logic input used to select the ADC. Use CS to select the

ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When

CS is high, the DOUT/RDY output is tristated.

ERROR

DI/O

Error Input/Output or General-Purpose Output. The ERROR pin can be used in one of the following

three modes:

Active low error input mode. This mode sets the ADC_ERROR bit in the status register.

Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.

The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error

on any device can be observed.

General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON

SYNC

Synchronization Input. Allows synchronization of the digital filters and analog modulators when using

multiple AD4116 devices.

IOVDD

Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is

independent of AVDD. For example, IOVDD can be operated at 3.3 V when AVDD equals 5 V, or vice

versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.

DGND

Digital Ground.

REGCAPD

Digital LDO Regulator Output. The REGCAPD pin is for decoupling purposes only. Decouple the

REGCAPD pin to DGND using a 1 µF capacitor.

GPIO0

DI/O

General-Purpose Input and Output 0. Logic input and output on the GPIO0 pin is referred to the AVDD

and AVSS supplies.

GPIO1

DI/O

General-Purpose Input and Output 1. Logic input and output on the GPIO1 pin is referred to the AVDD

and AVSS supplies.

GPO2

General-Purpose Output 2. Logic output on the GPIO2 pin is referred to the AVDD and AVSS supplies.

VIN4

Voltage Input 4. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN5 in differential configuration.

VIN5

Voltage Input 5. Input referenced to VINCOM in single ended configuration, or a negative input of an

input pair with VIN4 in differential configuration.

VIN6

Voltage Input 6. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN7 in differential configuration.

VIN7

Voltage Input 7. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN6 in differential configuration.

VIN8

Voltage Input 8. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN9 in differential configuration.

VIN9

Voltage Input 9. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN8 in differential configuration.

VIN10

Voltage Input 10. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VINCOM in differential configuration.

ADCIN11

Low Level ADC Input 11. Input referenced to ADCIN15 in pseudo differential input, or a positive input of

an input pair with ADCIN12 in differential configuration.

ADCIN12

Low Level ADC Input 12. Input referenced to ADCIN15 in pseudo differential input, or a negative input

of an input pair with ADCIN11 in differential configuration.

ADCIN13

Low Level ADC Input 13. Input referenced to ADCIN15 in pseudo differential input, or a positive input of

an input pair with ADCIN14 in differential configuration.

ADCIN14

Low Level ADC Input 14. Input referenced to ADCIN15 in pseudo differential input, or a negative input

of an input pair with ADCIN13 in differential configuration.

ADCIN15

Low Level ADC Input 15. Low level inputs are referenced to the ADCIN15 pin when configured as

pseudo differential input, or a negative input of an input pair with any of the low level input pins in a

differential input.

GPO3

General-Purpose Output 3. Logic output on the GPO3 pin is referred to the AVDD and AVSS supplies.

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