AD4116 datasheet(29/59 Pages) AD

29 / 59 page

Data Sheet

AD4116

Rev. 0 | Page 29 of 59

The no damage to device sections show the allowable positive

and negative voltages that can be applied to a voltage input pin

without exceeding the absolute maximum. The performance of

other channels is degraded, but the performance recovers when

the overvoltage is removed. This voltage range is specified as an

absolute maximum rating of ±65 V. Operation beyond the

maximum operating conditions for extended periods can affect

product reliability.

Low Level Inputs

The absolute, low level, input voltage in unbuffered mode

includes the range between AVSS − 50 mV and AVDD + 50 mV.

The absolute input voltage range in buffered mode is restricted

to a range between AVSS and AVDD. This low level input

voltage is specified with an absolute maximum rating of

AVSS − 0.3 V to AVDD1 + 0.3 V.

DATA OUTPUT CODING

Voltage Inputs

When the ADC is configured for unipolar operation, the

output code is natural (straight) binary with a zero differential

input voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111.

The output code for any input voltage is represented as

Code = (2N × VIN × 0.1)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any

analog input voltage can be represented as

Code = 2N − 1 × ((VIN × 0.1/VREF) + 1)

where:

N = 24.

VIN is the input voltage.

VREF is the reference voltage.

Low Level Inputs

When the ADC is configured for unipolar operation, the

output code is natural (straight) binary with a zero differential

input voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111. The output code for any low-

level input voltage is represented as

Code = (2N × VADCIN)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any low-

level input voltage is represented as

Code = 2N – 1 × ((VADCIN/VREF) + 1)

where:

N = 24.

VREF is the reference voltage.

VADCIN is the low level input voltage.

AD4116 REFERENCE

The AD4116 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device,

using AVDD − AVSS, or by allowing the use of the internal

2.5 V, low noise, low drift reference. Select the reference source

to be used by the analog input by setting the REF_SELx bits,

Bits[5:4], in the setup configuration registers appropriately. By

default, the AD4116 uses an external reference on power-up.

Internal Reference

The AD4116 includes a low noise, low drift voltage reference.

The internal reference has a 2.5 V output. The internal

reference is output on the REFOUT pin after the REF_EN bit in

the ADC mode register is set and is decoupled to AVSS with a

0.1 μF capacitor. The AD4116 internal reference is disabled by

default on power-up.

External Reference

The AD4116 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR4525, are recommended for

use. Apply the external reference to the AD4116 reference pins

as shown in Figure 42. Decouple the output of any external

reference to AVSS. As shown in Figure 42, the ADR4525

output is decoupled with a 0.1 μF capacitor at the output for

stability purposes. The output is then connected to a 4.7 μF

capacitor, which acts as a reservoir for any dynamic charge

required by the ADC and is followed by a 0.1 μF decoupling

capacitor at the REF+ input. This capacitor is placed as close as

possible to the REF+ and REF− pins.

The REF− pin is connected directly to the AVSS potential. When

an external reference is used instead of the internal reference

to supply the AD4116, attention must be paid to the output of

the REFOUT pin. The internal reference is controlled by the

REF_EN bit (Bit 15) in the ADC mode register. If the internal

reference is not being used elsewhere in the application, ensure

that the REF_EN bit is disabled.

AD4116 Datasheet(PDF) 29 Page - Analog Devices

AD4116 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL