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TPS37 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS37 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 48 page ![]() 7.7 Timing Diagrams VSENSEx Hysteresis tSD + tCTRx VPOR UVLO(MIN) VDD(MIN) VDD SENSEx VITN (UV) + VHYS VITN (UV) RESETx_UVxx tCTSx tCTRx *See Note C tSD + tCTRx RESETx_UVxx tCTSx tCTRx *See Note C t < tCTSx A. For open-drain output option, the timing diagram assumes the RESETx_UVOD / RESETx_UVOD pin is connected via an external pull-up resistor to VDD. B. Be advised that this diagram shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time. C. RESETx_UVxx / RESETx_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached. Figure 7-1. SENSEx Undervoltage (UV) Timing Diagram TPS37 SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS37 |
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