TPS37 datasheet(23/48 Pages) TI

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8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input

The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic

reference to (CTR1 / MR) and (CTR2 / MR). A logic low on MR causes RESET1 to assert on reset output.

After MR is left floating, RESET1 will release the reset if the voltage at SENSE1 pin is at nominal voltage. MR

should not be driven high, this pin should be left floating or connected to a capacitor to GND, this pin can be left

unconnected if is not used.

If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated

in Figure 8-8.

Low Voltage

High Voltage

Reset

Delay

CTRx

Active low

Logic

VDD

MCU

GPIO

Low or Floating

Figure 8-8. Manual Reset Implementation

CTRx/MR

RESETx

Active-High

VSENSEx

SENSE VOLTAGE WITH IN THRESHOLD

VITN < VSENSEx < VITP

< VMR

MR floating or

connected to capacitor

MR floating or

connected to capacitor

RESETx

Active-Low

Figure 8-9. Manual Reset Timing Diagram

Table 8-3. MR Functional Table

SENSE ON NOMINAL VOLTAGE

RESET STATUS

Low

Yes

Reset asserted

Floating

Yes

Fast reset release when SENSE

voltage goes back to nominal

voltage

Capacitor

Yes

Programmable reset time delay

High

Yes

NOT Recommended

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TPS37

SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021

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