TPS37 datasheet(16/48 Pages) TI

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8.3 Feature Description

8.3.1 Input Voltage (VDD)

VDD operating voltage ranges from 2.7 V to 65 V. An input supply capacitor is not required for this device;

however, if the input supply is noisy good analog practice is to place a 0.1 µF capacitor between the VDD and

GND.

VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional.

VDD voltage is independent of VSENSE and VRESET, meaning that VDD can be higher or lower than the other

pins.

8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)

When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (VPOR),

the output pins will be in reset, regardless of the voltage at SENSE pins.

8.3.1.2 Power-On Reset (VDD < VPOR )

When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is

not to be relied upon for proper device function.

VSENSEx

SENSE VOLTAGE OUTSIDE OF THRESHOLD

VITN > VSENSEx > VITP

Undefined

tSD+tCTRx

Undefined

Output stays low since VSENSEx

is outside of threshold

VDD

VDD(MIN)

UVLO(MIN)

VPOR

VOL

RESETx

Active Low

RESETx

Active High

Figure 8-2. Power Cycle (SENSE Outside of Nominal voltage) 2

2 Figure assumes an external pull-up resistor is connected to the reset pin via VDD

TPS37

SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021

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TPS37 Datasheet(PDF) 16 Page - Texas Instruments