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TPS37 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS37 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 48 page ![]() VSENSEx Hysteresis tSD + tCTRx VPOR UVLO(MIN) VDD(MIN) VDD SENSEx VITP (OV) - VHYS VITP (OV) RESETx_OVxx tCTSx tCTRx *See Note C tSD + tCTRx RESETx_OVxx tCTSx tCTRx *See Note C t < tCTSx A. For open-drain output option, the timing diagram assumes the RESETx_OVOD / RESETx_OVOD pin is connected via an external pull-up resistor to VDD. B. Be advised that this diagram shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time. C. RESETx_OVxx / RESETx_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached. Figure 7-2. SENSEx Overvoltage (OV) Timing Diagram www.ti.com TPS37 SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS37 |
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