LT4239 datasheet(10/24 Pages) AD

10 / 24 page

LT4239

Rev. 0

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In most high current Hot Swap applications, multiple

parallel MOSFETs are used to minimize the voltage drop,

power loss and accompanying temperature rise on the

pass transistors. Due to the gate threshold variation,

parallel MOSFETs driven by a single gate driver tend to

concentrate the current into a single MOSFET during initial

turn-on or current limit. As a result, expensive MOSFETs

with enough SOA to withstand such events are needed.

The LT4239 offers a low-cost solution by providing two

gate drivers to separately control the initial turn-on and

the power distribution. Only start-up MOSFET is needed

for initial turn-on and one or more parallel MOSFETs with

low RDS(ON) bypass the start-up for power distribution.

The following sections cover turn-on, turn-off, and vari-

ous faults that the LT4239 detects and acts upon. External

component selection is discussed in detail in the Design

Example section.

APPLICATIONS INFORMATION

A typical LT4239 application circuit operating at 12V sup-

ply with a 100A load in a high availability system is shown

in Figure 1. The board power supply at the OUT pin is con-

trolled with external N-Channel MOSFETs (M1, M2) placed

in the power path. M1 is a trickle MOSFET for start-up

while M2 can be a group of parallel MOSFETs for passing

the power. The current through the MOSFETs is monitored

with sense resistors (RS1, RS2) connected on the source

side of the MOSFETs. Resistors R10 – R13 are part of the

sense resistor averaging network. Resistors R1 and R2 at

the UV pin define an undervoltage level of the input supply

to turn on the MOSFETs. RVCC and C1 protect the VCC pin

from input supply transient spikes and help holding up

the VCC voltage when the input supply collapses during

output short. The MOSFET’s drain voltage is monitored

through RDRAIN at the DRAIN pin. R3 and R4 prevent high

frequency self-oscillations in M1 and M2 respectively. The

R-C network, RG1 and CG1 at GATE1 pin limit the inrush

to the load capacitance during start-up.

M2A ×4

RDRAIN

100k

1µF

RS1

10m

RS2A

CG1

33nF

RG1

CST

2.2µF

R4A

×4

RVCC

13.7k

CLOAD

10mF

SENSE1 SENSE2

GATE1

DRAIN

STMR

CBTMR

OUT

OUTK

GATE2

FLT

LT4239

GND

IBOOST

IMON

VOUT

12V

100A

R10

R11

VCC

RS2B

R12

R13

R4B

×4

M2B ×4

0.1µF

CFT

47nF

4239 F01

ADC

Z1*: OPTIONAL (SMCJ33A)

M2A, M2B: PSMN1R0-25YLD

M1: PSMN6R1-30YLD

×6

10k

POWER GOOD

Z1*

12V

10k

12V

GND

BACKPLANE PLUG-IN

BOARD

Figure 1. Typical Application

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