LT4239 datasheet(11/24 Pages) AD

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LT4239

Rev. 0

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APPLICATIONS INFORMATION

Turn-On Sequence

Before the MOSFETs are turned on, the VCC supply must

exceed its 3.6V undervoltage lockout level. The N-Channel

MOSFETs are then turned on in two stages with dual gate

drive to pass the load current. When the input supply

rises above the UV undervoltage threshold set by a R1/

R2 divider, it initiates an internal 25ms debounce delay.

During the debounce cycle, the external MOSFET’s health

is monitored at the MOSFET’s drain and OUTK pin. If the

voltage difference is less than 1.3V indicating a MOSFET’s

drain/source short, FLT will be pulled low at the end of the

debounce cycle. Otherwise, the MOSFET M1 is turned on

first by charging up GATE1 with a 10µA current source from

the charge pump. Concurrently, STMR pin voltage will start

ramping up with a 10µA current source. Connect a capac-

itor from STMR to GND to set the total allowed start-up

time. The voltage at the GATE1 pin rises with a slope equal

to 10µA/CG1 and the inrush current flowing into the load

capacitor CLOAD is limited to (10µA/CG1) • CLOAD.

The OUT voltage follows GATE1 after M1 has reached its

threshold voltage. If too small of CG1 is used, the current

flowing through RS1 may become too high and reach

the current limit, which triggers an internally set 100µs

timer. When the timer expires, the FLT pin pulls low to

indicate a fault condition. With appropriate CG1 selected,

the current can be kept below the current limit allowing

GATE1 to charge up turning on M1. When the gate drive

for M1 exceeds 10V and the voltage difference between

the MOSFET’s drain and the OUTK pin is less than 1V,

GATE2 charges up with a 50µA current source.

As GATE2 rises, M2 turns on when its threshold voltage is

exceeded. When GATE2 is fully on and the voltage between

the MOSFET’s drain and the OUTK pin falls below 100mV,

GATE1 pulls down to OUT turning off M1. The STMR pin is

reset to ground by a 125µA current. A 10ms power-good

timer is initiated while GATE2 continues to charge up until

it is limited by the internal 12V clamp between GATE2 and

OUT. At the end of the timer delay, the PG is released to

pull high to indicate power is good and the load may be

activated. The capacitance value at the STMR pin should

be chosen such that the ramp-up period is long enough

for GATE2 to be started up successfully without STMR

reaching its fault threshold.

20ms/DIV

IINRUSH

2A/DIV

4239 F02

∆VGATE1

10V/DIV

∆VGATE2

10V/DIV

VOUT

10V/DIV

Figure 2. Normal Start-Up Waveforms

Turn-Off Sequence

A normal turn-off is initiated by pulling the UV pin below

its 1.182V threshold (50mV hysteresis). The MOSFETs

are turned off with 10mA currents pulling down the

GATE pins to OUT. Additionally, several fault conditions

can cause turn-off of the GATE pins. These include FET

short and FET-Bad detection as well as an extended over-

current condition either during start-up or after power

good. During output overcurrent fault condition, GATE2

is pulled down to OUT with 50mA. When a severe output

short is detected, either during inrush or normal operation

period, a current source of 130mA or 600mA pulls GATE1

or GATE2, respectively to OUT. If the VCC pin falls below

its 3.6V undervoltage lockout threshold, both GATE1 and

GATE2 pins are also pulled down to the OUT pin with

130mA and 600mA, respectively.

Constant Current Start-Up Using a GATE R-C Network

A R-C network must be used on the trickle MOSFET M1

for start-up. The series resistor and capacitor network

from GATE1 to ground (RG1 and CG1 in Figure 1) limits the

GATE1 slew rate and inrush current to less than the cur-

rent limit. The internal 100µs fault timer will not run since

the current limit is not engaged during start-up, which

allows the use of MOSFET with smaller safe operating

area for M1. RG1 should be chosen such that IGATE1(UP) •

RG1 is less than the MOSFET’s threshold voltage to avoid

a current spike at the beginning of start-up. Using a too

small value for RG1 can degrade the stability of the current

limit circuit. For proper operation, the value of RG1 should

be ≥ 470Ω and CG1 should be ≤ 100nF.

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