LT4239 datasheet(14/24 Pages) AD

14 / 24 page

LT4239

Rev. 0

For more information www.analog.com

terminals. If the GATE2 drive falls below its 10V threshold,

a FET-Bad condition is detected.

When either FET-Bad condition is present, an internal

20ms FET-Bad fault timer will be activated. The timer

resets whenever the FET-Bad condition disappears. After

the timer expires, the FLT pin pulls low and the GATE2 is

pulled down to OUT with a 10mA current. A FET-Bad fault

detection can only be cleared by lowering the VCC below

its 3.6V undervoltage lockout threshold.

FET Short Fault

The LT4239 monitors the integrity of the MOSFETs during

the debounce cycle. A FET short fault is detected if the

voltage between the MOSFET’s drain and OUTK pin

remains below 1.3V at the end of the 25ms debounce

cycle. The FLT pin will be pulled low after the debounce

cycle. The LT4239 will enter a cool-off period of 512 timing

cycles before the fault is cleared and the part can restart.

Resetting Faults

Faults generated during start-up or after power good will

cause the LT4239 to latch-off and FLT pin to be pulled low.

Pulling the UV pin below 0.6V will reset the latched fault.

If UV is pulled low during the cool-off period, it will not

reset the fault. But if UV continues to stay low until the

cool-off cycle is over, the fault will be reset at the end of

the cool-off period. If UV is pulled low after the cool-off

period, it will reset the fault instantly. When UV goes high

again after the fault latch is cleared, a debounce timing

cycle is initiated followed by GATE1 start-up.

The LT4239 can be configured for auto-retry by tying

the FLT to UV in a circuit shown in Figure 8. Whenever

the FLT pin is pulled low due to a fault, the UV pin will

also be pulled below 0.6V to reset the fault latch. For

faults that are followed by a cool-off cycle, the output will

only restart again at the end of the cool-off period when

the fault resets. However, for faults that don’t trigger the

cool-off cycle, the fault will be reset instantly allowing the

debounce timing cycle to restart. There is an exception

for a FET-Bad fault detected after power good, the FLT

pin will remain low prohibiting the debounce timing cycle

from starting.

Lowering the input supply until the VCC falls below its

undervoltage lockout threshold (3.6V) shuts off all the

MOSFETs and resets the fault latch. That includes reset-

ting the fault while the device in cool-off cycle.

Using IBOOST to Double the Circuit Breaker and

Current Limit Thresholds

The IBOOST pin can be used to double the circuit breaker,

current limit thresholds and the FET-Bad fault threshold

to ride through load surges after power good. It doesn’t

increase the current limit threshold of the start-up chan-

nel. Pulling the IBOOST pin above 1.6V will double those

thresholds allowing large current to pass through the pass

transistors without generating a fault. However, higher

current limit settings will result in higher MOSFET power

dissipation in the event of an output short. Proper choice

of the MOSFET must accommodate high power dissipa-

tion under the worst-case short-circuit if the IBOOST pin

function is used.

Monitor MOSFET Current

The current through the sense resistor RS2 is monitored

by LT4239’s current sense amplifier at the SENSE2 and

OUTK pins. See Figure 4. The sense amplifier is supplied

from the OUT voltage that must be greater than 3.7V for

the IMON output to be valid. An internal resistor RIN of

200Ω is connected between the amplifier’s negative input

terminal and SENSE2 pin. Another internal resistor ROUT

of 20k is connected between the IMON and GND pins.

The IMON output voltage is equal to (ROUT/RIN) • VSENSE.

The resistor ratio ROUT/RIN defines the voltage gain of the

sense amplifier and is set to 100. Full scale input sense

voltage to the sense amplifier is 30mV, corresponding

to an output of 3V at IMON pin. For input supply voltage

greater than 5V, the output clamps at 4.9V if the allow-

able input sense voltage range is exceeded. The IMON

pin is held at ground potential if the OUT voltage is less

than 3.7V.

A capacitor connected from the IMON pin to GND will

reduce noise at the output and may also be useful as a

charge reservoir to keep the pin steady while driving a

switching circuit such as an ADC.

APPLICATIONS INFORMATION

LT4239 Datasheet(PDF) 14 Page - Analog Devices

LT4239 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL