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LT4239 Datasheet(PDF) 18 Page - Analog Devices

Part # LT4239
Description  High Current Hot Swap Controller with Current Monitor Output
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LT4239 Datasheet(HTML) 18 Page - Analog Devices

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LT4239
18
Rev. 0
For more information www.analog.com
In addition, a resistor RDRAIN of 100kΩ with1% tolerance
is placed on the DRAIN pin for sensing the MOSFET’s
drain voltage accurately. A RC filter consisting of a 1kΩ
resistor and a 1µF ceramic bypass capacitor is also placed
on the VCC pin so that TVS is not required from the input
supply to ground.
Layout Considerations
To achieve accurate current sensing, Kelvin connections
for the sense resistors are required. The PCB layout of
Kelvin sensing traces should be balanced and symmetri-
cal to balance the parasitics on the PCB. Even with a good
PCB layout, it is necessary to use a resistor network to
average the voltages sensed across the individual parallel
sense resistors. In the 12V/100A application shown in
Figure 11, the SENSE2 and OUTK pins of the LT4239 are
joined to the six 0.5mΩ sense resistors with an array of
1Ω resistors. The resulting voltage between the SENSE2
and OUTK pins is the average of all the voltages across
the 0.5mΩ sense resistors, effectively Kelvin sensing the
six 0.5mΩ resistors. The same arrangement can also be
expanded for Kelvin sensing twelve 1mΩ resistors. The
Kelvin sensing connection from RS1 10mΩ is not con-
nected to OUTK so as not to affect the effective sense
resistance between the SENSE2 and OUTK pins. A rec-
ommended PCB layout is shown in Figure 6.
The PCB traces associated with the power path through
the MOSFETs should have low resistance. The suggested
trace width for 2oz copper foil is 0.01-inch per ampere
or wider to keep PCB trace resistance, voltage drop, and
temperature rise to a minimum. Note that 2oz copper foil
exhibits a sheet resistance of about 0.25mΩ/square. Small
resistances add up quickly in high current applications.
To improve noise immunity, place the resistive divider to
the UV pin close to the device and keep traces to supply
input and GND short. It is also important to place the
bypass capacitor C1 as close as possible between VCC and
ground. A 0.1µF capacitor C2 from the UV pin to ground
also helps reject supply noise. The 100kΩ resistor RDRAIN
for monitoring the MOSFET’s drain voltage should also be
placed near the DRAIN pin. If a surge suppressor, Z1, is
used, it should be placed between the IN and OUT using
wide traces.
APPLICATIONS INFORMATION
Try to avoid placing the ground plane immediately under
the power MOSFETs. If the MOSFETs fail and overheat, that
could result in a catastrophic failure as the input supply gets
shorted to ground when the insulation between them fails.
M2
RS5
CURRENT FLOW
TO LOAD
VIA TO GND PLANE
R18
R19
•••
•••
RS4
R16
R17
•••
•••
RS3
R14
R15
•••
•••
RS2
R12
R13
•••
•••
R6
•••
M3
R7
•••
M4
R8
•••
M5
R9
•••
RS7
R22
R23
•••
•••
RS6
R20
R21
•••
•••
OUT
IN
•••
•••
•••
RVCC
RDRAIN
SENSE2
OUTK
GATE2
C1
4239 F06
16
15
14
13
12
11
10
9
17
1
2
3
4
5
6
7
8
LT4239
Figure 6. Recommended Layout



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