AD5413 datasheet(31/49 Pages) AD

31 / 49 page

Data Sheet

AD5413

Rev. 0 | Page 31 of 49

To calculate the decimal value that is written to the internal

DAC register (DACCODE), use the following equation:

(1)

CODE

DAC









where:

D is the code loaded to the DAC_INPUT register.

M is the code in the USER_GAIN register (default code = 214 − 1).

C is the code in the USER_OFFSET register (default code = 213).

Data from the DAC_INPUT register is processed by a digital

multiplier and adder, which are controlled by the contents of the

USER_GAIN register and USER_OFFSET register, respectively.

The calibrated DAC data is loaded to the DAC. The DAC data

loading depends on the state of the LDAC pin.

Each time data is written to the USER_GAIN register or USER_

OFFSET register, the DAC output is not automatically updated.

Instead, the next write to the DAC_INPUT register uses these user

gain and user offset values to perform a new calibration and

automatically update the output channel. The read only DAC_

OUTPUT register represents the value currently loaded into the

DAC before any user gain or user offset calibrations are applied.

The USER_GAIN register and the USER_OFFSET register both

have 14 bits of resolution. Always calibrate the gain first and then

calibrate the offset.

DAC OUTPUT UPDATE AND DATA INTEGRITY

DIAGNOSTICS

Figure 64 shows a simplified version of the DAC input loading

circuitry. If the gain and offset are used, update the USER_

GAIN register and USER_OFFSET register before writing to the

DAC_INPUT register.

VIOUT

INTERFACE LOGIC

OUTPUT

AMPLIFIER

SDO

SDI

14-BIT

DAC

REFIN

SYNC

LDAC

(HARDWARE OR SOFTWARE)

DAC INPUT

USER

GAIN AND OFFSET

CALIBRATION

SCLK

DAC OUTPUT

(READ ONLY)

CLEAR CODE

CLEAR

EVENT

Figure 64. Simplified Serial Interface of Input Loading Circuitry

The DAC_OUTPUT register and the DAC output update in

any of the following cases:



If a write is performed on the DAC_INPUT register with

the hardware LDAC pin tied low, the DAC_OUTPUT

to the timing specifications in Table 3.



If a write is performed on the DAC_INPUT register with

the hardware LDAC pin tied high, the DAC_OUTPUT

is issued or the hardware LDAC pin is pulsed low.



If the slew rate control feature is enabled, the DAC_

OUTPUT register contains the dynamic value of the DAC

as the register slews between values.

The GP_CONFIG2 register contains a bit to enable a global

software LDAC active low mode that ignores the AD5413 address

bits of the SW_LDAC command, which enables multiple AD5413

devices to be simultaneously updated with a single SW_LDAC

command. This feature is useful if the hardware LDAC pin is

not being used in a system containing multiple AD5413 devices.

DAC Data Integrity Diagnostics

To protect against transient changes to the internal digital circuitry,

the digital block stores both the digital DAC value and an inverted

copy of the digital DAC value. A check is completed to ensure that

the two values correspond to each other before the DAC is strobed

to update to the DAC code. This matching feature is enabled by

default via the INVERSE_DAC_CHECK_EN bit in the DIGITAL_

DIAG_CONFIG register.

Outside of the digital block, the DAC code is stored in latches,

as shown in Figure 65. These latches are potentially vulnerable to

the same transient events that affect the digital block. To protect

the DAC latches against such transients, enable the DAC latch

monitor feature via the DAC_LATCH_MON_EN bit within the

DIGITAL_DIAG_CONFIG register. This latch monitor feature

monitors the actual digital code driving the DAC and compares

the code with the digital code generated within the digital block.

Any difference between the two codes sets the DAC_LATCH_

MON_ERR bit flag in the DIGITAL_DIAG_RESULTS register.

14-BIT

DAC

DIGITAL

BLOCK

DAC LATCHES

Figure 65. DAC Data Integrity

USE OF KEY CODES

Key codes are used via the key register to initiate calibration

memory refresh and initiate a software reset (see the Key

Using specific keys to initiate actions such as a calibration memory

refresh or a software reset provides extra system robustness

because the keys reduce the probability of either task being

initiated in error.

AD5413 Datasheet(PDF) 31 Page - Analog Devices

AD5413 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL