Data Sheet

AD5413

Rev. 0 | Page 45 of 49

Bits

Bit Name

Description

Reset

Access

11: the status register contents and the previous SPI frame instruction are alternately

available on SDO.

[4:0]

READBACK_SELECT

Select Readback Address for a Two-Stage Readback.

0x0

R/W

0x00: NOP register (default).

0x01: DAC_INPUT register.

0x02: DAC_OUTPUT register.

0x03: CLEAR_CODE register.

0x04: USER_GAIN register.

0x05: USER_OFFSET register.

0x06: DAC_CONFIG register.

0x07: SW_LDAC register.

0x08: KEY register.

0x09: GP_CONFIG1 register.

0x0A: GP_CONFIG2 register.

0x0B: reserved (do not select this option).

0x0C: reserved (do not select this option).

0x0D: reserved (do not select this option).

0x0E: reserved (do not select this option).

0x0F: reserved (do not select this option).

0x10: DIGITAL_DIAG_CONFIG register.

0x11: reserved (do not select this option).

0x12: FAULT_PIN_CONFIG register.

0x13: TWO_STAGE_READBACK_SELECT register.

0x14: DIGITAL_DIAG_RESULTS register.

0x15: ANALOG_DIAG_RESULTS register.

0x16: STATUS register.

0x17: CHIP_ID register.

0x18: FREQ_MONITOR register.

0x19: reserved (do not select this option).

0x1A: reserved (do not select this option).

0x1B: reserved (do not select this option).

0x1C: DEVICE_ID_3 register.

Digital Diagnostic Results Register

Address: 0x14, Reset: 0x14A000, Name: DIGITAL_DIAG_RESULTS

The DIGITAL_DIAG_RESULTS register contains an error flag for the on-chip digital diagnostic features, most of which are configurable using

the digital diagnostic configuration register. This register also contains a flag to indicate that a reset occurred, as well as a flag to indicate that the

calibration memory has not refreshed or that an invalid SPI access was attempted. With the exception of the CAL_MEM_UNREFRESHED and

SLEW_BUSY flags, a 1 must be written to all flags to update to the current value. The CAL_MEM_UNREFRESHED and SLEW_BUSY flags

automatically clear when the calibration memory refresh or output slew, respectively, is complete. When the corresponding enable bits in

the DIGITAL_DIAG_CONFIG register are not enabled, the respective flag bits read as zero.

Table 36. Bit Descriptions for DIGITAL_DIAG_RESULTS

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

[20:16]

REGISTER_ADDRESS

Register Address.

0x0

R

15

CAL_MEM_UNREFRESHED

Calibration Memory Unrefreshed Flag. Modifying the RANGE bits in the

DAC_CONFIG register initiates a calibration memory refresh that asserts this bit.

Unlike the R/W-1-C bits in this register, this bit automatically clears when the

calibration memory refresh completes.

0x1

R

0: calibration memory refreshes.

1: calibration memory is unrefreshed (default on power-up). This bit asserts if the

RANGE bits are modified in the DAC_CONFIG register.