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AD5413

Data Sheet

Rev. 0 | Page 34 of 49

AD5413 REGISTERS

The AD5413 is controlled and configured via the 20 on-chip

registers described in the Register Map section. Possible access

permissions include the following:



R/W is read or write.



R is read only.



R/W-1-C is read or write 1 to clear.



R0/W is read zero or write.

Reading from or writing to reserved registers is flagged as an

invalid SPI access (see Table 36). When accessing registers with

reserved bit fields, the default value of those bit fields must be

written. These values are listed in the reset column of Table 22

to Table 41.

WRITING TO REGISTERS

Use the format data frame in Table 16 when writing to any register.

By default, the SPI CRC is enabled, and the input register is 32 bits

wide with the last 8 bits corresponding to the CRC code. Only

frames that are exactly 32 bits wide are accepted as valid. If the

CRC is disabled, the input register is 24 bits wide, and 32-bit

frames are also accepted with the final 8 bits ignored. Table 17

describes the bit names and functions of Bits[D23:D16].

Bits[D15:D0] depend on the register that is being addressed.

READING FROM REGISTERS

The AD5413 options for readback modes that can be configured

in the TWO_STAGE_READBACK_SELECT register (see

Table 35) include the following:



Two-stage readback



Autostatus readback



Shared SYNC autostatus readback



Echo mode

Two-Stage Readback Mode

Two-stage readback mode consists of a write to the TWO_

STAGE_READBACK_SELECT register to select the register

location to be read back, followed by an NOP command. To

perform an NOP command, write all 0s to Bits[D15:D0] of the

NOP register. During the NOP command, the contents of the

selected register are available on the SDO pin in the data frame

format shown in Table 18. The user can also write a new

two-stage readback command during the second frame,

such that the corresponding new data is available on the SDO

pin in the subsequent frame (see Figure 66). Bits[D31:D30] (or

Bits[D23:D22] if SPI CRC is not enabled) = 0b10 and are used

as part of the synchronization during readback. The contents of

the first write instruction to the TWO_STAGE_READBACK_

SELECT register are shown in Table 19.

Autostatus Readback Mode

When autostatus readback mode is selected, the contents of the

status register are available on the SDO line during each SPI

transaction. When reading back the status register, the SDO

contents differ from the data frame format shown in Table 18.

The contents of the status register are shown in Table 20. Refer to

the example shown in Figure 67.

Configure the autostatus readback mode via the READBACK_

MODE bits in the TWO_STAGE_READBACK_SELECT register

(see the Two-Stage Readback Select Register section).

Shared SYNC Autostatus Readback Mode

The shared SYNC autostatus readback mode is a unique version

of the autostatus readback mode used to avoid SDO bus

contention when multiple AD5413 devices share the same SYNC

line. If this issue occurs, the AD5413 devices are distinguished

from each other using the hardware address pins, AD0 and AD1.

An internal flag is set after each valid write to a device and the flag

is cleared on the subsequent falling edge of SYNC. The shared

SYNC autostatus readback mode behaves in a similar manner to

the normal autostatus readback mode, except the device does

not output the status register contents on SDO when SYNC goes

low unless the internal flag is set, which occurs when the previous

SPI write is valid. Refer to the example shown in Figure 68.

Echo Mode

Echo mode behaves in a similar manner to the autostatus

readback mode, except that every second readback consists of an

echo of the previous command written to the AD5413. Echo

mode is useful for checking which SPI instruction is received in

the previous SPI frame. Refer to the example shown in Figure 69.

Table 16. Writing to a Register

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

[D15:D0]

AD1

AD0

REG_ADR4

REG_ADR3

REG_ADR2

REG_ADR1

REG_ADR0

Data

Table 17. Input Register Decode

Bit

Description

AD1

Slip Bit. This bit must equal the inverse of Bit D22 (the AD1 pin).

AD1, AD0

These bits are used in association with the external pins, AD1 and AD0, to determine which AD5413

device is being addressed by the system controller. Up to four unique devices can be addressed

corresponding to the AD1 and AD0 addresses of 0b00, 0b01, 0b10, and 0b11.

REG_ADR4, REG_ADR3, REG_ADR2,

REG_ADR1, REG_ADR0

These bits select which register is written to. See Table 21 for a summary of the available registers.

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