Data Sheet

AD5413

Rev. 0 | Page 47 of 49

Status Register

Address: 0x16, Reset: 0x160000, Name: STATUS

The STAUS register contains status bits, as well as the, OR'd analog and digital diagnostics and the FAULT pin status bits.

Table 38. Bit Descriptions for STATUS

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

20

DIG_DIAG_STATUS

This bit represents the result of a logical OR of the contents of Bits[15:0] in the DIGITAL_DIAG_

RESULTS register (except for the SLEW_BUSY bit). If any of these bits are high, the

DIG_DIAG_STATUS bit is high. Note that this bit is high on power-up because of the

active RESET_OCCURRED flag bit.

0x1

R

A quiet mode is also available (SPI_DIAG_QUIET_EN in the GP_CONFIG1 register), in which the

logical OR function only incorporates Bits[15:3] of the DIGITAL_DIAG_RESULTS register

(except for the SLEW_BUSY bit). If an SPI CRC, SPI slip bit, or SCLK count error occurs, the

DIG_DIAG_STATUS bit is not set high.

19

ANA_DIAG_STATUS

This bit represents the result of a logical OR of the contents of Bits[13:0] in the ANALOG_DIAG_

RESULTS register. If any bit in the ANALOG_DIAG_RESULTS register is high, the ANA_DIAG_

STATUS bit is high.

0x0

R

[18:0]

RESERVED

Reserved.

0x0

R

Chip ID Register

Address: 0x17, Reset: 0x170101, Name: CHIP_ID

The CHIP_ID register contains the chip ID of the die.

Table 39. Bit Descriptions for CHIP_ID

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

[20:16]

REGISTER_ADDRESS

Register Address.

0x0

R

[15:11]

RESERVED

Reserved.

0x0

R0

[10:8]

RESERVED

Reserved.

0x0

R0

[7:0]

DIE_CHIP_ID

These bits reflect the revision number of the die.

0x2

R

Frequency Monitor Register

Address: 0x18, Reset: 0x180000, Name: FREQ_MONITOR

An internal frequency monitor uses the MCLK to create a pulse at a frequency of 1 kHz (MCLK/10,000). This pulse increments a 16-bit counter.

The value of the counter is available to read in the FREQ_MONITOR register. The user can poll this register periodically and use it as a

diagnostic tool for MCLK (to monitor whether the oscillator is running) and to measure the frequency. This feature is enabled by default via the

FREQ_MON_EN bit in the DIGITAL_DIAG_CONFIG register and allows a robustness check of MCLK.

Table 40. Bit Descriptions for FREQ_MONITOR

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

[20:16]

REGISTER_ADDRESS

Register Address.

0x0

R

[15:0]

FREQ_MONITOR

Internal Clock Counter Value.

0x0

R