AD5413 datasheet(25/49 Pages) AD

25 / 49 page

Data Sheet

AD5413

Rev. 0 | Page 25 of 49

THEORY OF OPERATION

The AD5413 is a single-channel, 14-bit voltage and current

output DAC that meets the requirements of industrial factory

automation and process control applications. The device

provides a high precision, fully integrated, single-chip solution to

generate a unipolar current, bipolar current, or voltage output.

DAC ARCHITECTURE

The DAC core architecture of the AD5413 consists of a voltage

mode R-2R DAC ladder network. The DAC core voltage output

is converted to either a current output or a voltage output at the

VIOUT pin. Only one mode can be enabled at a time. The voltage

and current output stages are both supplied by the AVDD1 power

rail and the AVSS power rail.

Current Output Mode

When current output mode is enabled, the DAC voltage output is

converted to a current that is mirrored to the supply rail so that

the application only sees a current source output (see Figure 57).

An internal or external 13.7 kΩ RSET resistor can be used for the

voltage to current conversion.

VIOUT

RSET

AVSS

AVDD1

IOUT

OPEN FAULT

14-BIT

DAC

Figure 57. Voltage to Current Conversion Circuitry

Voltage Output Mode

When voltage output mode is enabled, the DAC voltage output

is buffered and scaled to output a software selectable, unipolar or

bipolar voltage range (see Figure 58).

The available voltage output range is ±10.5 V. A 20% overrange

feature is also available via the DAC_CONFIG register.

RANGE

SCALING

DAC

VOUT SHORT FAULT

+VSENSE

–VSENSE

VIOUT

Figure 58. Voltage Output Architecture

Reference

The AD5413 can operate with either an external or internal

reference. The reference input requires a 2.5 V reference for

specified performance. This input voltage is internally buffered

before being applied to the DAC.

The AD5413 has an integrated, buffered, 2.5 V voltage reference

that is externally available for use elsewhere within the system. To

use the internal reference to drive the DAC, connect the

REFOUT pin to the REFIN pin.

SPI

The AD5413 is controlled over a versatile, 4-wire SPI that

operates at clock rates of up to 50 MHz and is compatible with

SPI, QSPI, MICROWIRE, and DSP standards. Data coding is

always straight binary.

Input Shift Register

With the SPI CRC enabled (default state), the input shift register is

32 bits wide. Data is loaded to the device MSB first as a 32-bit word

under the control of SCLK. Data is clocked in on the falling edge of

SCLK. If the CRC is disabled, the serial interface reduces to 24 bits.

In this case, a 32-bit frame is still accepted, but the last 8 bits are

ignored. See the AD5413 Register section for full details on the

registers that can be addressed via the SPI interface.

Table 8. Writing to a Register (CRC Enabled)

MSB

LSB

D31

[D30:D29]

[D28:D24]

[D23:D8]

[D7:D0]

Slip bit

AD5413 address

Data

CRC

Transfer Function

Table 9 shows the ideal output voltage to AD5413 input code

relationship for straight binary data coding of the ±10.5 V output

range. The lower 2 bits are unused and must not be written to.

Table 9. Ideal Output Voltage to Input Code Relationship1

Digital Input, Straight Binary

Data Coding

Analog Output

MSB

LSB2

VOUT (V)

1111

11XX

10.5 × (8192/8192)

1111

10XX

10.5 × (8191/8192)

1000

0000

00XX

0000

01XX

−10.5 × (8191/8192)

0000

00XX

−10.5

1 Assuming a 2.5 V voltage reference.

2 X means do not write.

AD5413 Datasheet(PDF) 25 Page - Analog Devices

AD5413 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL