AD5413

Data Sheet

Rev. 0 | Page 42 of 49

Key Register

Address: 0x08, Reset: 0x080000, Name: KEY

The KEY register accepts specific key codes to perform tasks such as calibration memory refresh and software reset. Bits[15:0] of this

register always read back as 0x0000. All unlisted key codes are reserved.

Table 30. Bit Descriptions for KEY

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

[20:16]

REGISTER_ADDRESS

Register Address.

0x0

R

[15:0]

KEY_CODE

Key Code.

0x0

R0/W

0x15FA: first of two keys to initiate a software reset.

0xAF51: second of two keys to initiate a software reset.

0xFCBA: key to initiate a calibration memory refresh to the shadow registers. This key is only

valid the first time it is run and has no effect if subsequent writes occur within a given system

reset cycle.

General-Purpose Configuration 1 Register

Address: 0x09, Reset: 0x090204, Name: GP_CONFIG1

The GP_CONFIG1 register configures functions such as the temperature comparator threshold and enables other miscellaneous features.

Table 31. Bit Descriptions for GP_CONFIG1

Bits

Bit Name

Description

Reset

Access

21

FAULT_PIN_STATUS

This bit reflects the current status of the FAULT pin.

0x0

R

[20:16]

REGISTER_ADDRESS

Register Address.

0x0

R

[15:14]

RESERVED

Reserved.

0x0

R

[13:12]

SET_TEMP_THRESHOLD

Temperature Comparator Threshold Value Setting.

0x0

R/W

00: 142°C (default).

01: 127°C.

10: 112°C.

11: 97°C.

[11:10]

RESERVED

Reserved.

0x0

R/W

[9:7]

RESERVED

Reserved.

0x4

R/W

6

HART_EN

0x0

R/W

0: DAC output drives the output stage directly (default).

slew capacitor connection of a slew capacitor.

5

RESERVED

Reserved.

0x0

R/W

4

CLEAR_NOW_EN

Enables the clear code to update the DAC immediately, even if the output slew

feature is currently enabled.

0x0

R/W

0: disable (default).

1: enable.

3

SPI_DIAG_QUIET_EN

SPI Diagnostic Quiet Mode Enable. When this bit is enabled, the SPI_CRC_ERR,

SLIPBIT_ERR, and SCLK_COUNT_ERR bits are not included in the logical OR calculation,

which creates the DIG_DIAG_STATUS bit in the status register. These bits are also masked

from affecting the FAULT pin if this bit is set.

0x0

R/W

0: disable (default).

1: enable.

2

OSC_STOP_DETECT_EN

Enables automatic 0x07DEAD code on SDO if the MCLK stops.

0x1

R/W

0: disable.

1: enable (default).

1

RESERVED

Reserved.

0x0

R/W

0

VIOUT_PULLDOWN_EN

0x0

R/W

0: disable (default).

1: enable.