LTM4660 datasheet(20/28 Pages) AD

20 / 28 page

LTM4660

Rev. 0

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APPLICATIONS INFORMATION

contained within the μModule regulator, whereas green

resistances are external to the μModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a μModule. For example, in nor-

mal board-mounted applications, never does 100% of

the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bottom

of the μModule—as the standard defines for θJCtop and

θJCbottom, respectively. In practice, power loss is ther-

mally dissipated in both directions away from the pack-

age granted, in the absence of a heat sink and airflow, a

majority of the heat flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the μModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JSED 51-9 to predict power loss heat flow.

The LTM4660 package has been designed such that

inductor on top also doubles as a heat sink, removing heat

from the power switches below. The bottom substrate

material has very low thermal resistance to the printed

circuit board. An external heat sink can be applied to the

top of the device for excellent heat sinking with airflow.

Figure 12 shows a thermal capture of LTM4660 with 48V

input, 12V output at 25A without heat sink and 200LFM

airflow condition.

Recommended PCB footprint

The high integration of LTM4660 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND, VOUT. It helps to minimize the PCB

conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VIN, MID, GND and VOUT pins to mini-

mize high frequency noise.

• Use short loops to route CFLY capacitors from C+ to C–.

Reduce the parasitic trace inductance and resistance

in this loop.

JUNCTION

AMBIENT

Module DEVICE

4660 F11

θJCtop, JUNCTION-TO-CASE (TOP)

RESISTANCE

θJB, JUNCTION-TO-BOARD RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

θJCbot, JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

θJA, JUNCTION-TO-AMBIENT RESISTANCE

Figure 11. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms

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