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LMK04828SNKDREP Datasheet(PDF) 34 Page - Texas Instruments |
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LMK04828SNKDREP Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 102 page  R CLKinX CLKinX* N Phase Detector PLL1 External VCXO or Tunable Crystal R N Phase Detector PLL2 Dual Internal VCOs External Loop Filter OSCout OSCout* LMK0482x CPout2 Device Clock Divider Digital Delay Analog Delay SDCLKoutY SDCLKoutY* DCLKoutX DCLKoutX* Partially Integrated Loop Filter 7 Device Clocks External Loop Filter PLL1 PLL2 7 blocks Up to 3 inputs Input Buffer SYSREF Digital Delay Analog Delay 7 SYSREF or Device Clocks 1 Global SYSREF Divider Up to 1 OSCout Copyright © 2017, Texas Instruments Incorporated 34 LMK04828-EP SNAS703 – APRIL 2017 www.ti.com Product Folder Links: LMK04828-EP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 9.4 Device Functional Modes The following section describes the settings to enable various modes of operation for the LMK04828-EP. See Figure 7 and Figure 8 for visual diagrams of each mode. The LMK04828-EP is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device. 9.4.1 DUAL PLL Figure 12 illustrates the typical use case of the LMK04828-EP in dual loop mode. In dual loop mode the reference to PLL1 from CLKin0, CLKin1, or CLKin2. An external VCXO or tunable crystal is used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered through the OSCout port. The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs. Hitless switching and holdover functionality are optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal. It is also possible to use an external VCO in place of the internal VCO of the PLL2. In this case one less CLKin is available as a reference. Figure 12. Simplified Functional Block Diagram for Dual Loop Mode Table 6. Dual Loop Mode Register Configuration FIELD REGISTER ADDRESS FUNCTION VALUE SELECTED VALUE PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider 0 OSCin PLL2_NCLK_MUX 0x13F Selects the input to the PLL2 N divider 0 PLL2_P FB_MUX_EN 0x13F Enables the Feedback Mux 0 Disabled FB_MUX 0x13F Selects the output of the Feedback Mux X Don't care because FB_MUX is disabled OSCin_PD 0x140 Powers down the OSCin port 0 Powered up CLKin0_OUT_MUX 0x147 Selects where the output of CLKin0 is directed. 2 PLL1 CLKin1_OUT_MUX 0x147 Selects where the output of CLKin1 is directed. 2 PLL1 VCO_MUX 0x138 Selects the VCO 0, 1, or an external VCO 0 or 1 VCO 0 or VCO 1 |
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