LMK04828SNKDREP datasheet(7/102 Pages) TI

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LMK04828-EP

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SNAS703 – APRIL 2017

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Electrical Characteristics (continued)

(3.15 V < VCC < 3.45 V, –55 °C < TA < +105°C. Typical values at VCC = 3.3 V, TA = 25 °C, at the recommended operating

conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(4)

Assured by characterization.

(5)

This parameter is programmable.

(6)

FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.

(7)

Assured by characterization. ATE tested at 122.88 MHz.

(8)

The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS

fFBCLKin

Clock input frequency for

0-delay with external feedback.

AC-coupled

CLKinX_TYPE = 0 (Bipolar)

0.001

750

MHz

fFin

Clock input frequency for

external VCO mode

AC-coupled (4)

CLKinX_TYPE = 0 (Bipolar)

0.001

3100

MHz

Clock input frequency for

distribution mode

AC-coupled

CLKinX_TYPE = 0 (Bipolar)

0.001

3200

VFBCLKin/Fin

Single-ended clock input voltage

AC-coupled

CLKinX_TYPE = 0 (Bipolar)

0.25

Vpp

SLEWFBCLKin/Fin

Slew rate on CLKin (2)

AC-coupled; 20% to 80%;

(CLKinX_TYPE = 0)

0.15

0.5

V/ns

PLL1 SPECIFICATIONS

fPD1

PLL1 phase detector frequency

MHz

ICPout1SOURCE

PLL1 charge pump source current (5)

VCPout1 = VCC/2, PLL1_CP_GAIN = 0

µA

VCPout1 = VCC/2, PLL1_CP_GAIN = 1

150

VCPout1 = VCC/2, PLL1_CP_GAIN = 2

250

…

VCPout1 = VCC/2, PLL1_CP_GAIN = 14

1450

VCPout1 = VCC/2, PLL1_CP_GAIN = 15

1550

ICPout1SINK

PLL1 Charge pump sink current (5)

VCPout1=VCC/2, PLL1_CP_GAIN = 0

–50

µA

VCPout1=VCC/2, PLL1_CP_GAIN = 1

–150

VCPout1=VCC/2, PLL1_CP_GAIN = 2

–250

…

VCPout1=VCC/2, PLL1_CP_GAIN = 14

–1450

VCPout1=VCC/2, PLL1_CP_GAIN = 15

–1550

ICPout1%MIS

Charge pump sink / source mismatch

VCPout1 = VCC/2, T = 25 °C

10%

ICPout1VTUNE

Magnitude of charge pump current

variation vs. charge pump voltage

0.5 V < VCPout1 < VCC - 0.5 V

TA = 25 °C

ICPout1%TEMP

Charge pump current vs. temperature

variation

ICPout1TRI

Charge pump TRI-STATE leakage current 0.5 V < VCPout < VCC - 0.5 V

PN10kHz

PLL 1/f Noise at 10-kHz offset.

Normalized to 1-GHz Output Frequency

PLL1_CP_GAIN = 350 µA

–117

dBc/Hz

PLL1_CP_GAIN = 1550 µA

–118

PN1Hz

Normalized phase noise contribution

PLL1_CP_GAIN = 350 µA

–221.5

dBc/Hz

PLL1_CP_GAIN = 1550 µA

–223

PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS

fOSCin

PLL2 reference input (6)

500

MHz

SLEWOSCin

PLL2 reference clock minimum slew rate

on OSCin (2)

20% to 80%

0.15

0.5

V/ns

VOSCin

Input voltage for OSCin or OSCin*

AC-coupled; Single-ended

(Unused pin AC-coupled to GND)

0.2

2.4

Vpp

VIDOSCin

Differential voltage swing

See Figure 4

AC-coupled

0.2

1.55

|V|

VSSOSCin

0.4

3.1

Vpp

|VOSCin-offset|

DC offset voltage between

OSCin/OSCin* (OSCinX* - OSCinX)

Each pin is AC-coupled

|mV|

fdoubler_max

Doubler input frequency (7)

EN_PLL2_REF_2X = 1(8);

OSCin Duty Cycle 40% to 60%

155

MHz

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