LMK04828SNKDREP datasheet(18/102 Pages) TI

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LMK04828-EP

SNAS703 – APRIL 2017

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Overview (continued)

The VCXO or Crystal buffered output can be synchronized to the VCO clock distribution outputs by using

Cascaded 0-Delay Mode. The buffered output of VCXO/Crystal has deterministic phase relationship with CLKin.

9.1.5 Frequency Holdover

The LMK04828-EP supports holdover operation to keep the clock outputs on frequency with minimum drift when

the reference is lost until a valid reference clock signal is re-established.

9.1.6 PLL2 Integrated Loop Filter Poles

The LMK04828-EP features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors

and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter

response. The integrated programmable resistors and capacitors compliment external components mounted near

the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

9.1.7 Internal VCOs

The LMK04828-EP has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed to

the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler

and N-divider.

9.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04828-EP.

Using an external VCO reduces the number of available clock inputs by one.

9.1.9 Clock Distribution

The LMK04828-EP features a total of 14 PLL2 clock outputs driven from the internal or external VCO.

All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL, LVDS, or HSDS,

or LCPECL.

If OSCout is included in the total number of clock outputs the LMK04828-EP is able to distribute, then up to 15

differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

9.1.9.1 Device Clock Divider

Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32

(even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this divider may also

be directed to SDCLKoutY, where Y = X + 1.

9.1.9.2 SYSREF Clock Divider

The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191

(even and odd).

9.1.9.3 Device Clock Delay

The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.

The analog delay allows a nominal 25 ps step size and range from 0 to 575 ps of total delay. Enabling the analog

delay adds a nominal 500 ps of delay in addition to the programmed value.

The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles. The delay step can be as

small as half the period of the clock distribution path. For example, 2-GHz VCO frequency results in 250-ps

coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

LMK04828SNKDREP Datasheet(PDF) 18 Page - Texas Instruments

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