LMK04828SNKDREP datasheet(4/102 Pages) TI

4 / 102 page

LMK04828-EP

SNAS703 – APRIL 2017

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Product Folder Links: LMK04828-EP

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Pin Functions (continued)

I/O

TYPE

DESCRIPTION

(1)

NO.

NAME

SYNC/SYSREF_REQ

CMOS

Synchronization input or SYSREF_REQ for requesting continuous SYSREF

7, 8, 9

Do not connect. These pins must be left floating.

Vcc1_VCO

PWR

Power supply for VCO LDO

LDObyp1

ANLG

LDO bypass, bypassed to ground with 10-µF capacitor.

LDObyp2

ANLG

LDO bypass, bypassed to ground with a 0.1-µF capacitor.

SDCLKout3,

SDCLKout3*

Programmable

SYSREF or device clock output 3

DCLKout2,

DCLKout2*

Programmable

Device clock output 2

Vcc2_CG1

PWR

Power supply for clock outputs 2 and 3

CS*

CMOS

Chip select

SCK

CMOS

SPI clock

SDIO

I/O

CMOS

SPI data

Vcc3_SYSREF

PWR

Power supply for SYSREF divider and SYNC

SDCLKout5,

SDCKLout5*

Programmable

SYSREF or device clock output 5

DCLKout4,

DCLKout4*

Programmable

Device clock output 4

Vcc4_CG2

PWR

Power supply for clock outputs 4, 5, 6 and 7

DCLKout6,

DCLKout6*

Programmable

Device clock output 6

SDCLKout7,

SDCLKout7*

Programmable

SYSREF or device clock output 7

Status_LD1

I/O

Programmable

Programmable status pin

CPout1

ANLG

Charge pump 1 output

Vcc5_DIG

PWR

Power supply for the digital circuitry

CLKin1, CLKin1*

ANLG

Reference clock Input Port 1 for PLL1

FBCLKin,

FBCLKin*

ANLG

Feedback input for external clock feedback input (0–delay mode)

Fin, Fin*

ANLG

External VCO input (external VCO mode)

Vcc6_PLL1

PWR

Power supply for PLL1, charge pump 1, holdover DAC

CLKin0, CLKin0*

ANLG

Reference clock input port 0 for PLL1

Vcc7_OSCout

PWR

Power supply for OSCout port

OSCout, OSCout*

I/O

Programmable

Buffered output of OSCin port

CLKin2, CLKin2*

Reference clock Input Port 2 for PLL1

Vcc8_OSCin

PWR

Power supply for OSCin

OSCin, OSCin*

ANLG

Feedback to PLL1, reference input to PLL2 — AC-coupled

Vcc9_CP2

PWR

Power supply for PLL2 charge pump

CPout2

ANLG

Charge pump 2 output

Vcc10_PLL2

PWR

Power supply for PLL2

Status_LD2

I/O

Programmable

Programmable status pin

SDCLKout9,

SDCLKout9*

Programmable

SYSREF or device clock 9

DCLKout8,

DCLKout8*

Programmable

Device clock output 8

Vcc11_CG3

PWR

Power supply for clock outputs 8, 9, 10, and 11

DCLKout10,

DCLKout10*

Programmable

Device clock output 10

SDCLKout11,

SDCLKout11*

Programmable

SYSREF or device clock output 11

CLKin_SEL0

I/O

Programmable

Programmable status pin

CLKin_SEL1

I/O

Programmable

Programmable status pin

SDCLKout13,

SDCLKout13*

Programmable

SYSREF or device clock output 13

DCLKout12,

DCLKout12*

Programmable

Device clock output 12

Vcc12_CG0

PWR

Power supply for clock outputs 0, 1, 12, and 13

DAP

GND

DIE ATTACH PAD, connect to GND

LMK04828SNKDREP Datasheet(PDF) 4 Page - Texas Instruments

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