LMK04828SNKDREP datasheet(10/102 Pages) TI

10 / 102 page

LMK04828-EP

SNAS703 – APRIL 2017

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Electrical Characteristics (continued)

(3.15 V < VCC < 3.45 V, –55 °C < TA < +105°C. Typical values at VCC = 3.3 V, TA = 25 °C, at the recommended operating

conditions and are not assured.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(14) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(15) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid

for delay mode.

(16) LVPECL uses a 120-Ω emitter resistor, LVDS and HSDS use a 560-Ω shunt.

CLKout CLOSED LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO (13)

JCLKout

LMK04828-EP, VCO0

fCLKout = 245.76 MHz

Integrated RMS jitter (12)

LVDS, BW = 100 Hz to 20 MHz

112

fs rms

LVDS, BW = 12 kHz to 20 MHz

109

HSDS 8 mA, BW = 100 Hz to 20 MHz

102

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 with 240 Ω,

BW = 100 Hz to 20 MHz

LVPECL20 with 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL with 240 Ω,

BW = 100 Hz to 20 MHz

LCPECL with 240 Ω,

BW = 12 kHz to 20 MHz

LMK04828-EP, VCO1

fCLKout = 245.76 MHz

Integrated RMS jitter (12)

LVDS, BW = 100 Hz to 20 MHz

108

fs rms

LVDS, BW = 12 kHz to 20 MHz

105

HSDS 8 mA, BW = 100 Hz to 20 MHz

HSDS 8 mA, BW = 12 kHz to 20 MHz

LVPECL16 with 240 Ω,

BW = 100 Hz to 20 MHz

LVPECL20 with 240 Ω,

BW = 12 kHz to 20 MHz

LCPECL with 240 Ω,

BW = 100 Hz to 20 MHz

LCPECL with 240 Ω,

BW = 12 kHz to 20 MHz

DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY

fCLKout-start-up

Default output clock frequency at device

power on (14)

LMK04828-EP

315

MHz

fOSCout

OSCout frequency

See (7)

500

MHz

CLOCK SKEW AND DELAY

|TSKEW|

DCLKoutX to SDCLKoutY

FCLK = 245.76 MHz, RL= 100 Ω

AC-coupled (15)

Same pair, same format(16)

SDCLKoutY_MUX = 0 (device clock)

|ps|

Maximum DCLKoutX or SDCLKoutY

to DCLKoutX or SDCLKoutY

FCLK = 245.76 MHz, RL= 100 Ω

AC-coupled

Any pair, same format (16)

SDCLKoutY_MUX = 0 (device clock)

tsJESD204B

SYSREF to device clock setup time base

reference.

See SYSREF to Device Clock Alignment

to adjust SYSREF to device clock setup

time as required.

SDCLKoutY_MUX = 1 (SYSREF)

SYSREF_DIV = 30

SYSREF_DDLY = 8 (global)

SDCLKoutY_DDLY = 1 (2 cycles, local)

DCLKoutX_MUX = 1 (Div + DCC + HS)

DCLKoutX_DIV = 30

DCLKoutX_DDLY_CNTH = 7

DCLKoutX_DDLY_CNTL = 6

DCLKoutX_HS = 0

SDCLKoutY_HS = 0

–80

tPDCLKin0_

SDCLKout1

Propagation delay from CLKin0 to

SDCLKout1

CLKin0_OUT_MUX = 0 (SYSREF Mux)

SYSREF_CLKin0_MUX = 1 (CLKin0)

SDCLKout1_PD = 0

SDCLKout1_DDLY = 0 (Bypass)

SDCLKout1_MUX = 1 (SR)

EN_SYNC = 1

LVPECL16 with 240 Ω

0.65

fADLYmax

Maximum analog delay frequency

DCLKoutX_MUX = 4

1536

MHz

LMK04828SNKDREP Datasheet(PDF) 10 Page - Texas Instruments

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